diff options
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h | 599 |
1 files changed, 599 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h new file mode 100644 index 00000000..122956bb --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h | |||
@@ -0,0 +1,599 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | /* | ||
23 | * Function naming determines intended use: | ||
24 | * | ||
25 | * <x>_r(void) : Returns the offset for register <x>. | ||
26 | * | ||
27 | * <x>_o(void) : Returns the offset for element <x>. | ||
28 | * | ||
29 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
30 | * | ||
31 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
32 | * | ||
33 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
34 | * and masked to place it at field <y> of register <x>. This value | ||
35 | * can be |'d with others to produce a full register value for | ||
36 | * register <x>. | ||
37 | * | ||
38 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
39 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
40 | * register <x>. | ||
41 | * | ||
42 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
43 | * to place it at field <y> of register <x>. This value can be |'d | ||
44 | * with others to produce a full register value for <x>. | ||
45 | * | ||
46 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
47 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
48 | * This value is suitable for direct comparison with other unshifted | ||
49 | * values appropriate for use in field <y> of register <x>. | ||
50 | * | ||
51 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
52 | * field <y> of register <x>. This value is suitable for direct | ||
53 | * comparison with unshifted values appropriate for use in field <y> | ||
54 | * of register <x>. | ||
55 | */ | ||
56 | #ifndef _hw_falcon_gv100_h_ | ||
57 | #define _hw_falcon_gv100_h_ | ||
58 | |||
59 | static inline u32 falcon_falcon_irqsset_r(void) | ||
60 | { | ||
61 | return 0x00000000U; | ||
62 | } | ||
63 | static inline u32 falcon_falcon_irqsset_swgen0_set_f(void) | ||
64 | { | ||
65 | return 0x40U; | ||
66 | } | ||
67 | static inline u32 falcon_falcon_irqsclr_r(void) | ||
68 | { | ||
69 | return 0x00000004U; | ||
70 | } | ||
71 | static inline u32 falcon_falcon_irqstat_r(void) | ||
72 | { | ||
73 | return 0x00000008U; | ||
74 | } | ||
75 | static inline u32 falcon_falcon_irqstat_halt_true_f(void) | ||
76 | { | ||
77 | return 0x10U; | ||
78 | } | ||
79 | static inline u32 falcon_falcon_irqstat_exterr_true_f(void) | ||
80 | { | ||
81 | return 0x20U; | ||
82 | } | ||
83 | static inline u32 falcon_falcon_irqstat_swgen0_true_f(void) | ||
84 | { | ||
85 | return 0x40U; | ||
86 | } | ||
87 | static inline u32 falcon_falcon_irqmode_r(void) | ||
88 | { | ||
89 | return 0x0000000cU; | ||
90 | } | ||
91 | static inline u32 falcon_falcon_irqmset_r(void) | ||
92 | { | ||
93 | return 0x00000010U; | ||
94 | } | ||
95 | static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v) | ||
96 | { | ||
97 | return (v & 0x1U) << 0U; | ||
98 | } | ||
99 | static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v) | ||
100 | { | ||
101 | return (v & 0x1U) << 1U; | ||
102 | } | ||
103 | static inline u32 falcon_falcon_irqmset_mthd_f(u32 v) | ||
104 | { | ||
105 | return (v & 0x1U) << 2U; | ||
106 | } | ||
107 | static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v) | ||
108 | { | ||
109 | return (v & 0x1U) << 3U; | ||
110 | } | ||
111 | static inline u32 falcon_falcon_irqmset_halt_f(u32 v) | ||
112 | { | ||
113 | return (v & 0x1U) << 4U; | ||
114 | } | ||
115 | static inline u32 falcon_falcon_irqmset_exterr_f(u32 v) | ||
116 | { | ||
117 | return (v & 0x1U) << 5U; | ||
118 | } | ||
119 | static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v) | ||
120 | { | ||
121 | return (v & 0x1U) << 6U; | ||
122 | } | ||
123 | static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v) | ||
124 | { | ||
125 | return (v & 0x1U) << 7U; | ||
126 | } | ||
127 | static inline u32 falcon_falcon_irqmclr_r(void) | ||
128 | { | ||
129 | return 0x00000014U; | ||
130 | } | ||
131 | static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v) | ||
132 | { | ||
133 | return (v & 0x1U) << 0U; | ||
134 | } | ||
135 | static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v) | ||
136 | { | ||
137 | return (v & 0x1U) << 1U; | ||
138 | } | ||
139 | static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v) | ||
140 | { | ||
141 | return (v & 0x1U) << 2U; | ||
142 | } | ||
143 | static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v) | ||
144 | { | ||
145 | return (v & 0x1U) << 3U; | ||
146 | } | ||
147 | static inline u32 falcon_falcon_irqmclr_halt_f(u32 v) | ||
148 | { | ||
149 | return (v & 0x1U) << 4U; | ||
150 | } | ||
151 | static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v) | ||
152 | { | ||
153 | return (v & 0x1U) << 5U; | ||
154 | } | ||
155 | static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v) | ||
156 | { | ||
157 | return (v & 0x1U) << 6U; | ||
158 | } | ||
159 | static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v) | ||
160 | { | ||
161 | return (v & 0x1U) << 7U; | ||
162 | } | ||
163 | static inline u32 falcon_falcon_irqmclr_ext_f(u32 v) | ||
164 | { | ||
165 | return (v & 0xffU) << 8U; | ||
166 | } | ||
167 | static inline u32 falcon_falcon_irqmask_r(void) | ||
168 | { | ||
169 | return 0x00000018U; | ||
170 | } | ||
171 | static inline u32 falcon_falcon_irqdest_r(void) | ||
172 | { | ||
173 | return 0x0000001cU; | ||
174 | } | ||
175 | static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v) | ||
176 | { | ||
177 | return (v & 0x1U) << 0U; | ||
178 | } | ||
179 | static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v) | ||
180 | { | ||
181 | return (v & 0x1U) << 1U; | ||
182 | } | ||
183 | static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v) | ||
184 | { | ||
185 | return (v & 0x1U) << 2U; | ||
186 | } | ||
187 | static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v) | ||
188 | { | ||
189 | return (v & 0x1U) << 3U; | ||
190 | } | ||
191 | static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v) | ||
192 | { | ||
193 | return (v & 0x1U) << 4U; | ||
194 | } | ||
195 | static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v) | ||
196 | { | ||
197 | return (v & 0x1U) << 5U; | ||
198 | } | ||
199 | static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v) | ||
200 | { | ||
201 | return (v & 0x1U) << 6U; | ||
202 | } | ||
203 | static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v) | ||
204 | { | ||
205 | return (v & 0x1U) << 7U; | ||
206 | } | ||
207 | static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v) | ||
208 | { | ||
209 | return (v & 0xffU) << 8U; | ||
210 | } | ||
211 | static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v) | ||
212 | { | ||
213 | return (v & 0x1U) << 16U; | ||
214 | } | ||
215 | static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v) | ||
216 | { | ||
217 | return (v & 0x1U) << 17U; | ||
218 | } | ||
219 | static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v) | ||
220 | { | ||
221 | return (v & 0x1U) << 18U; | ||
222 | } | ||
223 | static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v) | ||
224 | { | ||
225 | return (v & 0x1U) << 19U; | ||
226 | } | ||
227 | static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v) | ||
228 | { | ||
229 | return (v & 0x1U) << 20U; | ||
230 | } | ||
231 | static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v) | ||
232 | { | ||
233 | return (v & 0x1U) << 21U; | ||
234 | } | ||
235 | static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v) | ||
236 | { | ||
237 | return (v & 0x1U) << 22U; | ||
238 | } | ||
239 | static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v) | ||
240 | { | ||
241 | return (v & 0x1U) << 23U; | ||
242 | } | ||
243 | static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v) | ||
244 | { | ||
245 | return (v & 0xffU) << 24U; | ||
246 | } | ||
247 | static inline u32 falcon_falcon_curctx_r(void) | ||
248 | { | ||
249 | return 0x00000050U; | ||
250 | } | ||
251 | static inline u32 falcon_falcon_nxtctx_r(void) | ||
252 | { | ||
253 | return 0x00000054U; | ||
254 | } | ||
255 | static inline u32 falcon_falcon_mailbox0_r(void) | ||
256 | { | ||
257 | return 0x00000040U; | ||
258 | } | ||
259 | static inline u32 falcon_falcon_mailbox1_r(void) | ||
260 | { | ||
261 | return 0x00000044U; | ||
262 | } | ||
263 | static inline u32 falcon_falcon_itfen_r(void) | ||
264 | { | ||
265 | return 0x00000048U; | ||
266 | } | ||
267 | static inline u32 falcon_falcon_itfen_ctxen_enable_f(void) | ||
268 | { | ||
269 | return 0x1U; | ||
270 | } | ||
271 | static inline u32 falcon_falcon_idlestate_r(void) | ||
272 | { | ||
273 | return 0x0000004cU; | ||
274 | } | ||
275 | static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r) | ||
276 | { | ||
277 | return (r >> 0U) & 0x1U; | ||
278 | } | ||
279 | static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r) | ||
280 | { | ||
281 | return (r >> 1U) & 0x7fffU; | ||
282 | } | ||
283 | static inline u32 falcon_falcon_os_r(void) | ||
284 | { | ||
285 | return 0x00000080U; | ||
286 | } | ||
287 | static inline u32 falcon_falcon_engctl_r(void) | ||
288 | { | ||
289 | return 0x000000a4U; | ||
290 | } | ||
291 | static inline u32 falcon_falcon_cpuctl_r(void) | ||
292 | { | ||
293 | return 0x00000100U; | ||
294 | } | ||
295 | static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v) | ||
296 | { | ||
297 | return (v & 0x1U) << 1U; | ||
298 | } | ||
299 | static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v) | ||
300 | { | ||
301 | return (v & 0x1U) << 2U; | ||
302 | } | ||
303 | static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v) | ||
304 | { | ||
305 | return (v & 0x1U) << 3U; | ||
306 | } | ||
307 | static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v) | ||
308 | { | ||
309 | return (v & 0x1U) << 4U; | ||
310 | } | ||
311 | static inline u32 falcon_falcon_cpuctl_halt_intr_m(void) | ||
312 | { | ||
313 | return 0x1U << 4U; | ||
314 | } | ||
315 | static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r) | ||
316 | { | ||
317 | return (r >> 4U) & 0x1U; | ||
318 | } | ||
319 | static inline u32 falcon_falcon_cpuctl_stopped_m(void) | ||
320 | { | ||
321 | return 0x1U << 5U; | ||
322 | } | ||
323 | static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v) | ||
324 | { | ||
325 | return (v & 0x1U) << 6U; | ||
326 | } | ||
327 | static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_m(void) | ||
328 | { | ||
329 | return 0x1U << 6U; | ||
330 | } | ||
331 | static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_v(u32 r) | ||
332 | { | ||
333 | return (r >> 6U) & 0x1U; | ||
334 | } | ||
335 | static inline u32 falcon_falcon_cpuctl_alias_r(void) | ||
336 | { | ||
337 | return 0x00000130U; | ||
338 | } | ||
339 | static inline u32 falcon_falcon_cpuctl_alias_startcpu_f(u32 v) | ||
340 | { | ||
341 | return (v & 0x1U) << 1U; | ||
342 | } | ||
343 | static inline u32 falcon_falcon_imemc_r(u32 i) | ||
344 | { | ||
345 | return 0x00000180U + i*16U; | ||
346 | } | ||
347 | static inline u32 falcon_falcon_imemc_offs_f(u32 v) | ||
348 | { | ||
349 | return (v & 0x3fU) << 2U; | ||
350 | } | ||
351 | static inline u32 falcon_falcon_imemc_blk_f(u32 v) | ||
352 | { | ||
353 | return (v & 0xffU) << 8U; | ||
354 | } | ||
355 | static inline u32 falcon_falcon_imemc_aincw_f(u32 v) | ||
356 | { | ||
357 | return (v & 0x1U) << 24U; | ||
358 | } | ||
359 | static inline u32 falcon_falcon_imemd_r(u32 i) | ||
360 | { | ||
361 | return 0x00000184U + i*16U; | ||
362 | } | ||
363 | static inline u32 falcon_falcon_imemt_r(u32 i) | ||
364 | { | ||
365 | return 0x00000188U + i*16U; | ||
366 | } | ||
367 | static inline u32 falcon_falcon_sctl_r(void) | ||
368 | { | ||
369 | return 0x00000240U; | ||
370 | } | ||
371 | static inline u32 falcon_falcon_mmu_phys_sec_r(void) | ||
372 | { | ||
373 | return 0x00100ce4U; | ||
374 | } | ||
375 | static inline u32 falcon_falcon_bootvec_r(void) | ||
376 | { | ||
377 | return 0x00000104U; | ||
378 | } | ||
379 | static inline u32 falcon_falcon_bootvec_vec_f(u32 v) | ||
380 | { | ||
381 | return (v & 0xffffffffU) << 0U; | ||
382 | } | ||
383 | static inline u32 falcon_falcon_dmactl_r(void) | ||
384 | { | ||
385 | return 0x0000010cU; | ||
386 | } | ||
387 | static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void) | ||
388 | { | ||
389 | return 0x1U << 1U; | ||
390 | } | ||
391 | static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void) | ||
392 | { | ||
393 | return 0x1U << 2U; | ||
394 | } | ||
395 | static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v) | ||
396 | { | ||
397 | return (v & 0x1U) << 0U; | ||
398 | } | ||
399 | static inline u32 falcon_falcon_hwcfg_r(void) | ||
400 | { | ||
401 | return 0x00000108U; | ||
402 | } | ||
403 | static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r) | ||
404 | { | ||
405 | return (r >> 0U) & 0x1ffU; | ||
406 | } | ||
407 | static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r) | ||
408 | { | ||
409 | return (r >> 9U) & 0x1ffU; | ||
410 | } | ||
411 | static inline u32 falcon_falcon_dmatrfbase_r(void) | ||
412 | { | ||
413 | return 0x00000110U; | ||
414 | } | ||
415 | static inline u32 falcon_falcon_dmatrfbase1_r(void) | ||
416 | { | ||
417 | return 0x00000128U; | ||
418 | } | ||
419 | static inline u32 falcon_falcon_dmatrfmoffs_r(void) | ||
420 | { | ||
421 | return 0x00000114U; | ||
422 | } | ||
423 | static inline u32 falcon_falcon_dmatrfcmd_r(void) | ||
424 | { | ||
425 | return 0x00000118U; | ||
426 | } | ||
427 | static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v) | ||
428 | { | ||
429 | return (v & 0x1U) << 4U; | ||
430 | } | ||
431 | static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v) | ||
432 | { | ||
433 | return (v & 0x1U) << 5U; | ||
434 | } | ||
435 | static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v) | ||
436 | { | ||
437 | return (v & 0x7U) << 8U; | ||
438 | } | ||
439 | static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v) | ||
440 | { | ||
441 | return (v & 0x7U) << 12U; | ||
442 | } | ||
443 | static inline u32 falcon_falcon_dmatrffboffs_r(void) | ||
444 | { | ||
445 | return 0x0000011cU; | ||
446 | } | ||
447 | static inline u32 falcon_falcon_imctl_debug_r(void) | ||
448 | { | ||
449 | return 0x0000015cU; | ||
450 | } | ||
451 | static inline u32 falcon_falcon_imctl_debug_addr_blk_f(u32 v) | ||
452 | { | ||
453 | return (v & 0xffffffU) << 0U; | ||
454 | } | ||
455 | static inline u32 falcon_falcon_imctl_debug_cmd_f(u32 v) | ||
456 | { | ||
457 | return (v & 0x7U) << 24U; | ||
458 | } | ||
459 | static inline u32 falcon_falcon_imstat_r(void) | ||
460 | { | ||
461 | return 0x00000144U; | ||
462 | } | ||
463 | static inline u32 falcon_falcon_traceidx_r(void) | ||
464 | { | ||
465 | return 0x00000148U; | ||
466 | } | ||
467 | static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r) | ||
468 | { | ||
469 | return (r >> 16U) & 0xffU; | ||
470 | } | ||
471 | static inline u32 falcon_falcon_traceidx_idx_f(u32 v) | ||
472 | { | ||
473 | return (v & 0xffU) << 0U; | ||
474 | } | ||
475 | static inline u32 falcon_falcon_tracepc_r(void) | ||
476 | { | ||
477 | return 0x0000014cU; | ||
478 | } | ||
479 | static inline u32 falcon_falcon_tracepc_pc_v(u32 r) | ||
480 | { | ||
481 | return (r >> 0U) & 0xffffffU; | ||
482 | } | ||
483 | static inline u32 falcon_falcon_exterraddr_r(void) | ||
484 | { | ||
485 | return 0x00000168U; | ||
486 | } | ||
487 | static inline u32 falcon_falcon_exterrstat_r(void) | ||
488 | { | ||
489 | return 0x0000016cU; | ||
490 | } | ||
491 | static inline u32 falcon_falcon_exterrstat_valid_m(void) | ||
492 | { | ||
493 | return 0x1U << 31U; | ||
494 | } | ||
495 | static inline u32 falcon_falcon_exterrstat_valid_v(u32 r) | ||
496 | { | ||
497 | return (r >> 31U) & 0x1U; | ||
498 | } | ||
499 | static inline u32 falcon_falcon_exterrstat_valid_true_v(void) | ||
500 | { | ||
501 | return 0x00000001U; | ||
502 | } | ||
503 | static inline u32 falcon_falcon_icd_cmd_r(void) | ||
504 | { | ||
505 | return 0x00000200U; | ||
506 | } | ||
507 | static inline u32 falcon_falcon_icd_cmd_opc_s(void) | ||
508 | { | ||
509 | return 4U; | ||
510 | } | ||
511 | static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v) | ||
512 | { | ||
513 | return (v & 0xfU) << 0U; | ||
514 | } | ||
515 | static inline u32 falcon_falcon_icd_cmd_opc_m(void) | ||
516 | { | ||
517 | return 0xfU << 0U; | ||
518 | } | ||
519 | static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r) | ||
520 | { | ||
521 | return (r >> 0U) & 0xfU; | ||
522 | } | ||
523 | static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void) | ||
524 | { | ||
525 | return 0x8U; | ||
526 | } | ||
527 | static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void) | ||
528 | { | ||
529 | return 0xeU; | ||
530 | } | ||
531 | static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v) | ||
532 | { | ||
533 | return (v & 0x1fU) << 8U; | ||
534 | } | ||
535 | static inline u32 falcon_falcon_icd_rdata_r(void) | ||
536 | { | ||
537 | return 0x0000020cU; | ||
538 | } | ||
539 | static inline u32 falcon_falcon_dmemc_r(u32 i) | ||
540 | { | ||
541 | return 0x000001c0U + i*8U; | ||
542 | } | ||
543 | static inline u32 falcon_falcon_dmemc_offs_f(u32 v) | ||
544 | { | ||
545 | return (v & 0x3fU) << 2U; | ||
546 | } | ||
547 | static inline u32 falcon_falcon_dmemc_offs_m(void) | ||
548 | { | ||
549 | return 0x3fU << 2U; | ||
550 | } | ||
551 | static inline u32 falcon_falcon_dmemc_blk_f(u32 v) | ||
552 | { | ||
553 | return (v & 0xffU) << 8U; | ||
554 | } | ||
555 | static inline u32 falcon_falcon_dmemc_blk_m(void) | ||
556 | { | ||
557 | return 0xffU << 8U; | ||
558 | } | ||
559 | static inline u32 falcon_falcon_dmemc_aincw_f(u32 v) | ||
560 | { | ||
561 | return (v & 0x1U) << 24U; | ||
562 | } | ||
563 | static inline u32 falcon_falcon_dmemc_aincr_f(u32 v) | ||
564 | { | ||
565 | return (v & 0x1U) << 25U; | ||
566 | } | ||
567 | static inline u32 falcon_falcon_dmemd_r(u32 i) | ||
568 | { | ||
569 | return 0x000001c4U + i*8U; | ||
570 | } | ||
571 | static inline u32 falcon_falcon_debug1_r(void) | ||
572 | { | ||
573 | return 0x00000090U; | ||
574 | } | ||
575 | static inline u32 falcon_falcon_debug1_ctxsw_mode_s(void) | ||
576 | { | ||
577 | return 1U; | ||
578 | } | ||
579 | static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v) | ||
580 | { | ||
581 | return (v & 0x1U) << 16U; | ||
582 | } | ||
583 | static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void) | ||
584 | { | ||
585 | return 0x1U << 16U; | ||
586 | } | ||
587 | static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r) | ||
588 | { | ||
589 | return (r >> 16U) & 0x1U; | ||
590 | } | ||
591 | static inline u32 falcon_falcon_debug1_ctxsw_mode_init_f(void) | ||
592 | { | ||
593 | return 0x0U; | ||
594 | } | ||
595 | static inline u32 falcon_falcon_debuginfo_r(void) | ||
596 | { | ||
597 | return 0x00000094U; | ||
598 | } | ||
599 | #endif | ||