diff options
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mc_gk20a.c | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 12 |
3 files changed, 17 insertions, 13 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c index 107c851c..65f1a119 100644 --- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GK20A Master Control | 2 | * GK20A Master Control |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -88,6 +88,12 @@ irqreturn_t mc_gk20a_intr_thread_stall(struct gk20a *g) | |||
88 | 88 | ||
89 | gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); | 89 | gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); |
90 | 90 | ||
91 | /* handle critical interrupts first */ | ||
92 | if (mc_intr_0 & mc_intr_0_pbus_pending_f()) | ||
93 | gk20a_pbus_isr(g); | ||
94 | if (mc_intr_0 & mc_intr_0_priv_ring_pending_f()) | ||
95 | gk20a_priv_ring_isr(g); | ||
96 | |||
91 | for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) { | 97 | for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) { |
92 | active_engine_id = g->fifo.active_engines_list[engine_id_idx]; | 98 | active_engine_id = g->fifo.active_engines_list[engine_id_idx]; |
93 | 99 | ||
@@ -112,12 +118,8 @@ irqreturn_t mc_gk20a_intr_thread_stall(struct gk20a *g) | |||
112 | gk20a_fifo_isr(g); | 118 | gk20a_fifo_isr(g); |
113 | if (mc_intr_0 & mc_intr_0_pmu_pending_f()) | 119 | if (mc_intr_0 & mc_intr_0_pmu_pending_f()) |
114 | gk20a_pmu_isr(g); | 120 | gk20a_pmu_isr(g); |
115 | if (mc_intr_0 & mc_intr_0_priv_ring_pending_f()) | ||
116 | gk20a_priv_ring_isr(g); | ||
117 | if (mc_intr_0 & mc_intr_0_ltc_pending_f()) | 121 | if (mc_intr_0 & mc_intr_0_ltc_pending_f()) |
118 | g->ops.ltc.isr(g); | 122 | g->ops.ltc.isr(g); |
119 | if (mc_intr_0 & mc_intr_0_pbus_pending_f()) | ||
120 | gk20a_pbus_isr(g); | ||
121 | 123 | ||
122 | /* sync handled irq counter before re-enabling interrupts */ | 124 | /* sync handled irq counter before re-enabling interrupts */ |
123 | atomic_set(&g->sw_irq_stall_last_handled, hw_irq_count); | 125 | atomic_set(&g->sw_irq_stall_last_handled, hw_irq_count); |
diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c index a44df1e8..90bd95ac 100644 --- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c | |||
@@ -76,8 +76,6 @@ void gk20a_priv_ring_isr(struct gk20a *g) | |||
76 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); | 76 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); |
77 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | 77 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); |
78 | 78 | ||
79 | if (platform->is_fmodel) | ||
80 | return; | ||
81 | 79 | ||
82 | status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r()); | 80 | status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r()); |
83 | status1 = gk20a_readl(g, pri_ringmaster_intr_status1_r()); | 81 | status1 = gk20a_readl(g, pri_ringmaster_intr_status1_r()); |
@@ -90,7 +88,6 @@ void gk20a_priv_ring_isr(struct gk20a *g) | |||
90 | pri_ringmaster_intr_status0_overflow_fault_v(status0) != 0) { | 88 | pri_ringmaster_intr_status0_overflow_fault_v(status0) != 0) { |
91 | gk20a_reset_priv_ring(g); | 89 | gk20a_reset_priv_ring(g); |
92 | } | 90 | } |
93 | |||
94 | if (pri_ringmaster_intr_status0_gbl_write_error_sys_v(status0) != 0) { | 91 | if (pri_ringmaster_intr_status0_gbl_write_error_sys_v(status0) != 0) { |
95 | gk20a_dbg(gpu_dbg_intr, "SYS write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", | 92 | gk20a_dbg(gpu_dbg_intr, "SYS write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", |
96 | gk20a_readl(g, pri_ringstation_sys_priv_error_adr_r()), | 93 | gk20a_readl(g, pri_ringstation_sys_priv_error_adr_r()), |
@@ -109,6 +106,9 @@ void gk20a_priv_ring_isr(struct gk20a *g) | |||
109 | } | 106 | } |
110 | } | 107 | } |
111 | 108 | ||
109 | if (platform->is_fmodel) | ||
110 | return; | ||
111 | |||
112 | cmd = gk20a_readl(g, pri_ringmaster_command_r()); | 112 | cmd = gk20a_readl(g, pri_ringmaster_command_r()); |
113 | cmd = set_field(cmd, pri_ringmaster_command_cmd_m(), | 113 | cmd = set_field(cmd, pri_ringmaster_command_cmd_m(), |
114 | pri_ringmaster_command_cmd_ack_interrupt_f()); | 114 | pri_ringmaster_command_cmd_ack_interrupt_f()); |
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c index 76848159..3f066c37 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GP20B master | 2 | * GP20B master |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -113,6 +113,12 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) | |||
113 | 113 | ||
114 | gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); | 114 | gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); |
115 | 115 | ||
116 | /* handle critical interrupts first */ | ||
117 | if (mc_intr_0 & mc_intr_pbus_pending_f()) | ||
118 | gk20a_pbus_isr(g); | ||
119 | if (mc_intr_0 & mc_intr_priv_ring_pending_f()) | ||
120 | gk20a_priv_ring_isr(g); | ||
121 | |||
116 | for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) { | 122 | for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) { |
117 | active_engine_id = g->fifo.active_engines_list[engine_id_idx]; | 123 | active_engine_id = g->fifo.active_engines_list[engine_id_idx]; |
118 | 124 | ||
@@ -137,12 +143,8 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) | |||
137 | gk20a_fifo_isr(g); | 143 | gk20a_fifo_isr(g); |
138 | if (mc_intr_0 & mc_intr_pmu_pending_f()) | 144 | if (mc_intr_0 & mc_intr_pmu_pending_f()) |
139 | gk20a_pmu_isr(g); | 145 | gk20a_pmu_isr(g); |
140 | if (mc_intr_0 & mc_intr_priv_ring_pending_f()) | ||
141 | gk20a_priv_ring_isr(g); | ||
142 | if (mc_intr_0 & mc_intr_ltc_pending_f()) | 146 | if (mc_intr_0 & mc_intr_ltc_pending_f()) |
143 | g->ops.ltc.isr(g); | 147 | g->ops.ltc.isr(g); |
144 | if (mc_intr_0 & mc_intr_pbus_pending_f()) | ||
145 | gk20a_pbus_isr(g); | ||
146 | 148 | ||
147 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), | 149 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), |
148 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); | 150 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); |