diff options
-rw-r--r-- | drivers/gpu/nvgpu/Makefile | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/dbg_vgpu.c | 74 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/vgpu.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/vgpu.h | 2 | ||||
-rw-r--r-- | include/linux/tegra_vgpu.h | 24 |
5 files changed, 101 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 966c5eea..f6b3a673 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile | |||
@@ -77,6 +77,7 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ | |||
77 | vgpu/mm_vgpu.o \ | 77 | vgpu/mm_vgpu.o \ |
78 | vgpu/debug_vgpu.o \ | 78 | vgpu/debug_vgpu.o \ |
79 | vgpu/vgpu.o \ | 79 | vgpu/vgpu.o \ |
80 | vgpu/dbg_vgpu.o \ | ||
80 | vgpu/gk20a/vgpu_hal_gk20a.o \ | 81 | vgpu/gk20a/vgpu_hal_gk20a.o \ |
81 | vgpu/gk20a/vgpu_gr_gk20a.o \ | 82 | vgpu/gk20a/vgpu_gr_gk20a.o \ |
82 | vgpu/gm20b/vgpu_hal_gm20b.o \ | 83 | vgpu/gm20b/vgpu_hal_gm20b.o \ |
diff --git a/drivers/gpu/nvgpu/vgpu/dbg_vgpu.c b/drivers/gpu/nvgpu/vgpu/dbg_vgpu.c new file mode 100644 index 00000000..ef12c3fd --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/dbg_vgpu.c | |||
@@ -0,0 +1,74 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #include <linux/tegra_gr_comm.h> | ||
18 | #include <linux/tegra_vgpu.h> | ||
19 | |||
20 | #include "gk20a/gk20a.h" | ||
21 | #include "gk20a/channel_gk20a.h" | ||
22 | #include "gk20a/dbg_gpu_gk20a.h" | ||
23 | #include "vgpu.h" | ||
24 | |||
25 | static int vgpu_exec_regops(struct dbg_session_gk20a *dbg_s, | ||
26 | struct nvgpu_dbg_gpu_reg_op *ops, | ||
27 | u64 num_ops) | ||
28 | { | ||
29 | struct channel_gk20a *ch = dbg_s->ch; | ||
30 | struct gk20a_platform *platform = gk20a_get_platform(dbg_s->g->dev); | ||
31 | struct tegra_vgpu_cmd_msg msg; | ||
32 | struct tegra_vgpu_reg_ops_params *p = &msg.params.reg_ops; | ||
33 | void *oob; | ||
34 | size_t oob_size; | ||
35 | void *handle = NULL; | ||
36 | int ops_size, err = 0; | ||
37 | |||
38 | gk20a_dbg_fn(""); | ||
39 | BUG_ON(sizeof(*ops) != sizeof(struct tegra_vgpu_reg_op)); | ||
40 | |||
41 | handle = tegra_gr_comm_oob_get_ptr(TEGRA_GR_COMM_CTX_CLIENT, | ||
42 | tegra_gr_comm_get_server_vmid(), | ||
43 | TEGRA_VGPU_QUEUE_CMD, | ||
44 | &oob, &oob_size); | ||
45 | if (!handle) | ||
46 | return -EINVAL; | ||
47 | |||
48 | ops_size = sizeof(*ops) * num_ops; | ||
49 | if (oob_size < ops_size) { | ||
50 | err = -ENOMEM; | ||
51 | goto fail; | ||
52 | } | ||
53 | |||
54 | memcpy(oob, ops, ops_size); | ||
55 | |||
56 | msg.cmd = TEGRA_VGPU_CMD_REG_OPS; | ||
57 | msg.handle = platform->virt_handle; | ||
58 | p->handle = ch ? ch->virt_ctx : 0; | ||
59 | p->num_ops = num_ops; | ||
60 | p->is_profiler = dbg_s->is_profiler; | ||
61 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
62 | err = err ? err : msg.ret; | ||
63 | if (!err) | ||
64 | memcpy(ops, oob, ops_size); | ||
65 | |||
66 | fail: | ||
67 | tegra_gr_comm_oob_put_ptr(handle); | ||
68 | return err; | ||
69 | } | ||
70 | |||
71 | void vgpu_dbg_init(void) | ||
72 | { | ||
73 | dbg_gpu_session_ops_gk20a.exec_reg_ops = vgpu_exec_regops; | ||
74 | } | ||
diff --git a/drivers/gpu/nvgpu/vgpu/vgpu.c b/drivers/gpu/nvgpu/vgpu/vgpu.c index 6f91db4c..3791d8a7 100644 --- a/drivers/gpu/nvgpu/vgpu/vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/vgpu.c | |||
@@ -408,6 +408,7 @@ int vgpu_probe(struct platform_device *dev) | |||
408 | return err; | 408 | return err; |
409 | 409 | ||
410 | vgpu_init_support(dev); | 410 | vgpu_init_support(dev); |
411 | vgpu_dbg_init(); | ||
411 | 412 | ||
412 | init_rwsem(&gk20a->busy_lock); | 413 | init_rwsem(&gk20a->busy_lock); |
413 | 414 | ||
diff --git a/drivers/gpu/nvgpu/vgpu/vgpu.h b/drivers/gpu/nvgpu/vgpu/vgpu.h index ffb863cd..32f4b110 100644 --- a/drivers/gpu/nvgpu/vgpu/vgpu.h +++ b/drivers/gpu/nvgpu/vgpu/vgpu.h | |||
@@ -58,6 +58,8 @@ int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in, | |||
58 | void vgpu_init_hal_common(struct gk20a *g); | 58 | void vgpu_init_hal_common(struct gk20a *g); |
59 | int vgpu_gk20a_init_hal(struct gk20a *g); | 59 | int vgpu_gk20a_init_hal(struct gk20a *g); |
60 | int vgpu_gm20b_init_hal(struct gk20a *g); | 60 | int vgpu_gm20b_init_hal(struct gk20a *g); |
61 | |||
62 | void vgpu_dbg_init(void); | ||
61 | #else | 63 | #else |
62 | static inline int vgpu_pm_prepare_poweroff(struct device *dev) | 64 | static inline int vgpu_pm_prepare_poweroff(struct device *dev) |
63 | { | 65 | { |
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h index 4db3a16f..b0e25c60 100644 --- a/include/linux/tegra_vgpu.h +++ b/include/linux/tegra_vgpu.h | |||
@@ -72,7 +72,8 @@ enum { | |||
72 | TEGRA_VGPU_CMD_AS_MAP_EX, | 72 | TEGRA_VGPU_CMD_AS_MAP_EX, |
73 | TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS, | 73 | TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS, |
74 | TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE, | 74 | TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE, |
75 | TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE | 75 | TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE, |
76 | TEGRA_VGPU_CMD_REG_OPS | ||
76 | }; | 77 | }; |
77 | 78 | ||
78 | struct tegra_vgpu_connect_params { | 79 | struct tegra_vgpu_connect_params { |
@@ -271,6 +272,26 @@ struct tegra_vgpu_sm_debug_mode { | |||
271 | u32 enable; | 272 | u32 enable; |
272 | }; | 273 | }; |
273 | 274 | ||
275 | struct tegra_vgpu_reg_op { | ||
276 | u8 op; | ||
277 | u8 type; | ||
278 | u8 status; | ||
279 | u8 quad; | ||
280 | u32 group_mask; | ||
281 | u32 sub_group_mask; | ||
282 | u32 offset; | ||
283 | u32 value_lo; | ||
284 | u32 value_hi; | ||
285 | u32 and_n_mask_lo; | ||
286 | u32 and_n_mask_hi; | ||
287 | }; | ||
288 | |||
289 | struct tegra_vgpu_reg_ops_params { | ||
290 | u64 handle; | ||
291 | u64 num_ops; | ||
292 | u32 is_profiler; | ||
293 | }; | ||
294 | |||
274 | struct tegra_vgpu_cmd_msg { | 295 | struct tegra_vgpu_cmd_msg { |
275 | u32 cmd; | 296 | u32 cmd; |
276 | int ret; | 297 | int ret; |
@@ -297,6 +318,7 @@ struct tegra_vgpu_cmd_msg { | |||
297 | struct tegra_vgpu_gr_bind_ctxsw_buffers_params gr_bind_ctxsw_buffers; | 318 | struct tegra_vgpu_gr_bind_ctxsw_buffers_params gr_bind_ctxsw_buffers; |
298 | struct tegra_vgpu_mmu_debug_mode mmu_debug_mode; | 319 | struct tegra_vgpu_mmu_debug_mode mmu_debug_mode; |
299 | struct tegra_vgpu_sm_debug_mode sm_debug_mode; | 320 | struct tegra_vgpu_sm_debug_mode sm_debug_mode; |
321 | struct tegra_vgpu_reg_ops_params reg_ops; | ||
300 | char padding[192]; | 322 | char padding[192]; |
301 | } params; | 323 | } params; |
302 | }; | 324 | }; |