diff options
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index 54406008..8b70930a 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c | |||
@@ -22,7 +22,11 @@ | |||
22 | #include <linux/debugfs.h> | 22 | #include <linux/debugfs.h> |
23 | #include <linux/uaccess.h> | 23 | #include <linux/uaccess.h> |
24 | #include <linux/clk/tegra.h> | 24 | #include <linux/clk/tegra.h> |
25 | #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) | ||
26 | #include <soc/tegra/fuse.h> | ||
27 | #else | ||
25 | #include <linux/tegra-fuse.h> | 28 | #include <linux/tegra-fuse.h> |
29 | #endif | ||
26 | 30 | ||
27 | #include "gk20a/gk20a.h" | 31 | #include "gk20a/gk20a.h" |
28 | #include "hw_trim_gm20b.h" | 32 | #include "hw_trim_gm20b.h" |
@@ -240,6 +244,51 @@ found_match: | |||
240 | 244 | ||
241 | /* GPCPLL NA/DVFS mode methods */ | 245 | /* GPCPLL NA/DVFS mode methods */ |
242 | 246 | ||
247 | #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) | ||
248 | #define FUSE_RESERVED_CALIB 0x204 | ||
249 | |||
250 | static inline int fuse_get_gpcpll_adc_rev(u32 val) | ||
251 | { | ||
252 | return (val >> 30) & 0x3; | ||
253 | } | ||
254 | |||
255 | static inline int fuse_get_gpcpll_adc_slope_uv(u32 val) | ||
256 | { | ||
257 | /* Integer part in mV * 1000 + fractional part in uV */ | ||
258 | return ((val >> 24) & 0x3f) * 1000 + ((val >> 14) & 0x3ff); | ||
259 | } | ||
260 | |||
261 | static inline int fuse_get_gpcpll_adc_intercept_uv(u32 val) | ||
262 | { | ||
263 | /* Integer part in mV * 1000 + fractional part in 100uV */ | ||
264 | return ((val >> 4) & 0x3ff) * 1000 + ((val >> 0) & 0xf) * 100; | ||
265 | } | ||
266 | |||
267 | static int tegra_fuse_calib_gpcpll_get_adc(int *slope_uv, int *intercept_uv) | ||
268 | { | ||
269 | u32 val; | ||
270 | int ret; | ||
271 | |||
272 | ret = tegra_fuse_readl(FUSE_RESERVED_CALIB, &val); | ||
273 | if (ret) | ||
274 | return ret; | ||
275 | |||
276 | if (!fuse_get_gpcpll_adc_rev(val)) | ||
277 | return -EINVAL; | ||
278 | |||
279 | *slope_uv = fuse_get_gpcpll_adc_slope_uv(val); | ||
280 | *intercept_uv = fuse_get_gpcpll_adc_intercept_uv(val); | ||
281 | return 0; | ||
282 | } | ||
283 | |||
284 | #ifdef CONFIG_TEGRA_USE_NA_GPCPLL | ||
285 | static bool tegra_fuse_can_use_na_gpcpll(void) | ||
286 | { | ||
287 | return tegra_sku_info.gpu_speedo_id; | ||
288 | } | ||
289 | #endif | ||
290 | #endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) */ | ||
291 | |||
243 | /* | 292 | /* |
244 | * Read ADC characteristic parmeters from fuses. | 293 | * Read ADC characteristic parmeters from fuses. |
245 | * Determine clibration settings. | 294 | * Determine clibration settings. |