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-rw-r--r--drivers/gpu/nvgpu/common/pmu/pmu_pg.c4
-rw-r--r--drivers/gpu/nvgpu/lpwr/lpwr.c14
2 files changed, 6 insertions, 12 deletions
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_pg.c b/drivers/gpu/nvgpu/common/pmu/pmu_pg.c
index 3cdeedcc..ca74f243 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_pg.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_pg.c
@@ -206,7 +206,7 @@ int nvgpu_pmu_enable_elpg(struct gk20a *g)
206 pg_engine_id++) { 206 pg_engine_id++) {
207 207
208 if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_MS && 208 if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_MS &&
209 ACCESS_ONCE(pmu->mscg_stat) == PMU_MSCG_DISABLED) 209 pmu->mscg_stat == PMU_MSCG_DISABLED)
210 continue; 210 continue;
211 211
212 if (BIT(pg_engine_id) & pg_engine_id_list) 212 if (BIT(pg_engine_id) & pg_engine_id_list)
@@ -281,7 +281,7 @@ int nvgpu_pmu_disable_elpg(struct gk20a *g)
281 pg_engine_id++) { 281 pg_engine_id++) {
282 282
283 if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_MS && 283 if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_MS &&
284 ACCESS_ONCE(pmu->mscg_stat) == PMU_MSCG_DISABLED) 284 pmu->mscg_stat == PMU_MSCG_DISABLED)
285 continue; 285 continue;
286 286
287 if (BIT(pg_engine_id) & pg_engine_id_list) { 287 if (BIT(pg_engine_id) & pg_engine_id_list) {
diff --git a/drivers/gpu/nvgpu/lpwr/lpwr.c b/drivers/gpu/nvgpu/lpwr/lpwr.c
index c80ddee0..b1189590 100644
--- a/drivers/gpu/nvgpu/lpwr/lpwr.c
+++ b/drivers/gpu/nvgpu/lpwr/lpwr.c
@@ -352,11 +352,8 @@ int nvgpu_lpwr_enable_pg(struct gk20a *g, bool pstate_lock)
352 is_mscg_supported = nvgpu_lpwr_is_mscg_supported(g, 352 is_mscg_supported = nvgpu_lpwr_is_mscg_supported(g,
353 present_pstate); 353 present_pstate);
354 if (is_mscg_supported && g->mscg_enabled) { 354 if (is_mscg_supported && g->mscg_enabled) {
355 if (!ACCESS_ONCE(pmu->mscg_stat)) { 355 if (!pmu->mscg_stat)
356 WRITE_ONCE(pmu->mscg_stat, PMU_MSCG_ENABLED); 356 pmu->mscg_stat = PMU_MSCG_ENABLED;
357 /* make status visible */
358 smp_mb();
359 }
360 } 357 }
361 358
362 is_rppg_supported = nvgpu_lpwr_is_rppg_supported(g, 359 is_rppg_supported = nvgpu_lpwr_is_rppg_supported(g,
@@ -402,11 +399,8 @@ int nvgpu_lpwr_disable_pg(struct gk20a *g, bool pstate_lock)
402 is_mscg_supported = nvgpu_lpwr_is_mscg_supported(g, 399 is_mscg_supported = nvgpu_lpwr_is_mscg_supported(g,
403 present_pstate); 400 present_pstate);
404 if (is_mscg_supported && g->mscg_enabled) { 401 if (is_mscg_supported && g->mscg_enabled) {
405 if (ACCESS_ONCE(pmu->mscg_stat)) { 402 if (pmu->mscg_stat)
406 WRITE_ONCE(pmu->mscg_stat, PMU_MSCG_DISABLED); 403 pmu->mscg_stat = PMU_MSCG_DISABLED;
407 /* make status visible */
408 smp_mb();
409 }
410 } 404 }
411 405
412exit_unlock: 406exit_unlock: