diff options
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/channel_gk20a.c | 34 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 24 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mm_gk20a.c | 81 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mm_gk20a.h | 4 |
4 files changed, 31 insertions, 112 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c index 6573d9ca..80cddb32 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c | |||
@@ -87,41 +87,13 @@ static void release_used_channel(struct fifo_gk20a *f, struct channel_gk20a *c) | |||
87 | 87 | ||
88 | int channel_gk20a_commit_va(struct channel_gk20a *c) | 88 | int channel_gk20a_commit_va(struct channel_gk20a *c) |
89 | { | 89 | { |
90 | u64 addr; | ||
91 | u32 addr_lo; | ||
92 | u32 addr_hi; | ||
93 | void *inst_ptr; | ||
94 | |||
95 | gk20a_dbg_fn(""); | 90 | gk20a_dbg_fn(""); |
96 | 91 | ||
97 | inst_ptr = c->inst_block.cpuva; | 92 | if (!c->inst_block.cpuva) |
98 | if (!inst_ptr) | ||
99 | return -ENOMEM; | 93 | return -ENOMEM; |
100 | 94 | ||
101 | addr = gk20a_mm_iova_addr(c->g, c->vm->pdes.sgt->sgl); | 95 | gk20a_init_inst_block(&c->inst_block, c->vm, |
102 | addr_lo = u64_lo32(addr >> 12); | 96 | c->vm->gmmu_page_sizes[gmmu_page_size_big]); |
103 | addr_hi = u64_hi32(addr); | ||
104 | |||
105 | gk20a_dbg_info("pde pa=0x%llx addr_lo=0x%x addr_hi=0x%x", | ||
106 | (u64)addr, addr_lo, addr_hi); | ||
107 | |||
108 | gk20a_mem_wr32(inst_ptr, ram_in_page_dir_base_lo_w(), | ||
109 | ram_in_page_dir_base_target_vid_mem_f() | | ||
110 | ram_in_page_dir_base_vol_true_f() | | ||
111 | ram_in_page_dir_base_lo_f(addr_lo)); | ||
112 | |||
113 | gk20a_mem_wr32(inst_ptr, ram_in_page_dir_base_hi_w(), | ||
114 | ram_in_page_dir_base_hi_f(addr_hi)); | ||
115 | |||
116 | gk20a_mem_wr32(inst_ptr, ram_in_adr_limit_lo_w(), | ||
117 | u64_lo32(c->vm->va_limit) | 0xFFF); | ||
118 | |||
119 | gk20a_mem_wr32(inst_ptr, ram_in_adr_limit_hi_w(), | ||
120 | ram_in_adr_limit_hi_f(u64_hi32(c->vm->va_limit))); | ||
121 | |||
122 | if (c->g->ops.mm.set_big_page_size) | ||
123 | c->g->ops.mm.set_big_page_size(c->g, inst_ptr, | ||
124 | c->vm->gmmu_page_sizes[gmmu_page_size_big]); | ||
125 | 97 | ||
126 | return 0; | 98 | return 0; |
127 | } | 99 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 8acc5b45..9e19fa53 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GK20A Graphics | 2 | * GK20A Graphics |
3 | * | 3 | * |
4 | * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2015, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -1684,33 +1684,13 @@ static int gr_gk20a_init_ctxsw_ucode_vaspace(struct gk20a *g) | |||
1684 | struct vm_gk20a *vm = &mm->pmu.vm; | 1684 | struct vm_gk20a *vm = &mm->pmu.vm; |
1685 | struct device *d = dev_from_gk20a(g); | 1685 | struct device *d = dev_from_gk20a(g); |
1686 | struct gk20a_ctxsw_ucode_info *ucode_info = &g->ctxsw_ucode_info; | 1686 | struct gk20a_ctxsw_ucode_info *ucode_info = &g->ctxsw_ucode_info; |
1687 | void *inst_ptr; | ||
1688 | u32 pde_addr_lo; | ||
1689 | u32 pde_addr_hi; | ||
1690 | u64 pde_addr; | ||
1691 | int err; | 1687 | int err; |
1692 | 1688 | ||
1693 | err = gk20a_alloc_inst_block(g, &ucode_info->inst_blk_desc); | 1689 | err = gk20a_alloc_inst_block(g, &ucode_info->inst_blk_desc); |
1694 | if (err) | 1690 | if (err) |
1695 | return err; | 1691 | return err; |
1696 | 1692 | ||
1697 | inst_ptr = ucode_info->inst_blk_desc.cpuva; | 1693 | gk20a_init_inst_block(&ucode_info->inst_blk_desc, vm, 0); |
1698 | |||
1699 | /* Set inst block */ | ||
1700 | gk20a_mem_wr32(inst_ptr, ram_in_adr_limit_lo_w(), | ||
1701 | u64_lo32(vm->va_limit) | 0xFFF); | ||
1702 | gk20a_mem_wr32(inst_ptr, ram_in_adr_limit_hi_w(), | ||
1703 | ram_in_adr_limit_hi_f(u64_hi32(vm->va_limit))); | ||
1704 | |||
1705 | pde_addr = gk20a_mm_iova_addr(g, vm->pdes.sgt->sgl); | ||
1706 | pde_addr_lo = u64_lo32(pde_addr >> 12); | ||
1707 | pde_addr_hi = u64_hi32(pde_addr); | ||
1708 | gk20a_mem_wr32(inst_ptr, ram_in_page_dir_base_lo_w(), | ||
1709 | ram_in_page_dir_base_target_vid_mem_f() | | ||
1710 | ram_in_page_dir_base_vol_true_f() | | ||
1711 | ram_in_page_dir_base_lo_f(pde_addr_lo)); | ||
1712 | gk20a_mem_wr32(inst_ptr, ram_in_page_dir_base_hi_w(), | ||
1713 | ram_in_page_dir_base_hi_f(pde_addr_hi)); | ||
1714 | 1694 | ||
1715 | /* Map ucode surface to GMMU */ | 1695 | /* Map ucode surface to GMMU */ |
1716 | ucode_info->ucode_gpuva = gk20a_gmmu_map(vm, | 1696 | ucode_info->ucode_gpuva = gk20a_gmmu_map(vm, |
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c index 71b14d5b..8cd8e18c 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c | |||
@@ -2716,13 +2716,8 @@ void gk20a_free_inst_block(struct gk20a *g, struct inst_desc *inst_block) | |||
2716 | static int gk20a_init_bar1_vm(struct mm_gk20a *mm) | 2716 | static int gk20a_init_bar1_vm(struct mm_gk20a *mm) |
2717 | { | 2717 | { |
2718 | int err; | 2718 | int err; |
2719 | phys_addr_t inst_pa; | ||
2720 | void *inst_ptr; | ||
2721 | struct vm_gk20a *vm = &mm->bar1.vm; | 2719 | struct vm_gk20a *vm = &mm->bar1.vm; |
2722 | struct gk20a *g = gk20a_from_mm(mm); | 2720 | struct gk20a *g = gk20a_from_mm(mm); |
2723 | u64 pde_addr; | ||
2724 | u32 pde_addr_lo; | ||
2725 | u32 pde_addr_hi; | ||
2726 | struct inst_desc *inst_block = &mm->bar1.inst_block; | 2721 | struct inst_desc *inst_block = &mm->bar1.inst_block; |
2727 | u32 big_page_size = gk20a_get_platform(g->dev)->default_big_page_size; | 2722 | u32 big_page_size = gk20a_get_platform(g->dev)->default_big_page_size; |
2728 | 2723 | ||
@@ -2731,41 +2726,11 @@ static int gk20a_init_bar1_vm(struct mm_gk20a *mm) | |||
2731 | gk20a_init_vm(mm, vm, big_page_size, SZ_4K, | 2726 | gk20a_init_vm(mm, vm, big_page_size, SZ_4K, |
2732 | mm->bar1.aperture_size, false, "bar1"); | 2727 | mm->bar1.aperture_size, false, "bar1"); |
2733 | 2728 | ||
2734 | gk20a_dbg_info("pde pa=0x%llx", | ||
2735 | (u64)gk20a_mm_iova_addr(g, vm->pdes.sgt->sgl)); | ||
2736 | |||
2737 | pde_addr = gk20a_mm_iova_addr(g, vm->pdes.sgt->sgl); | ||
2738 | pde_addr_lo = u64_lo32(pde_addr >> ram_in_base_shift_v()); | ||
2739 | pde_addr_hi = u64_hi32(pde_addr); | ||
2740 | |||
2741 | err = gk20a_alloc_inst_block(g, inst_block); | 2729 | err = gk20a_alloc_inst_block(g, inst_block); |
2742 | if (err) | 2730 | if (err) |
2743 | goto clean_up_va; | 2731 | goto clean_up_va; |
2732 | gk20a_init_inst_block(inst_block, vm, big_page_size); | ||
2744 | 2733 | ||
2745 | inst_pa = inst_block->cpu_pa; | ||
2746 | inst_ptr = inst_block->cpuva; | ||
2747 | |||
2748 | gk20a_dbg_info("bar1 inst block physical phys = 0x%llx, kv = 0x%p", | ||
2749 | (u64)inst_pa, inst_ptr); | ||
2750 | |||
2751 | gk20a_mem_wr32(inst_ptr, ram_in_page_dir_base_lo_w(), | ||
2752 | ram_in_page_dir_base_target_vid_mem_f() | | ||
2753 | ram_in_page_dir_base_vol_true_f() | | ||
2754 | ram_in_page_dir_base_lo_f(pde_addr_lo)); | ||
2755 | |||
2756 | gk20a_mem_wr32(inst_ptr, ram_in_page_dir_base_hi_w(), | ||
2757 | ram_in_page_dir_base_hi_f(pde_addr_hi)); | ||
2758 | |||
2759 | gk20a_mem_wr32(inst_ptr, ram_in_adr_limit_lo_w(), | ||
2760 | u64_lo32(vm->va_limit) | 0xFFF); | ||
2761 | |||
2762 | gk20a_mem_wr32(inst_ptr, ram_in_adr_limit_hi_w(), | ||
2763 | ram_in_adr_limit_hi_f(u64_hi32(vm->va_limit))); | ||
2764 | |||
2765 | if (g->ops.mm.set_big_page_size) | ||
2766 | g->ops.mm.set_big_page_size(g, inst_ptr, big_page_size); | ||
2767 | |||
2768 | gk20a_dbg_info("bar1 inst block ptr: %08llx", (u64)inst_pa); | ||
2769 | return 0; | 2734 | return 0; |
2770 | 2735 | ||
2771 | clean_up_va: | 2736 | clean_up_va: |
@@ -2777,13 +2742,8 @@ clean_up_va: | |||
2777 | static int gk20a_init_system_vm(struct mm_gk20a *mm) | 2742 | static int gk20a_init_system_vm(struct mm_gk20a *mm) |
2778 | { | 2743 | { |
2779 | int err; | 2744 | int err; |
2780 | phys_addr_t inst_pa; | ||
2781 | void *inst_ptr; | ||
2782 | struct vm_gk20a *vm = &mm->pmu.vm; | 2745 | struct vm_gk20a *vm = &mm->pmu.vm; |
2783 | struct gk20a *g = gk20a_from_mm(mm); | 2746 | struct gk20a *g = gk20a_from_mm(mm); |
2784 | u64 pde_addr; | ||
2785 | u32 pde_addr_lo; | ||
2786 | u32 pde_addr_hi; | ||
2787 | struct inst_desc *inst_block = &mm->pmu.inst_block; | 2747 | struct inst_desc *inst_block = &mm->pmu.inst_block; |
2788 | u32 big_page_size = gk20a_get_platform(g->dev)->default_big_page_size; | 2748 | u32 big_page_size = gk20a_get_platform(g->dev)->default_big_page_size; |
2789 | 2749 | ||
@@ -2793,21 +2753,32 @@ static int gk20a_init_system_vm(struct mm_gk20a *mm) | |||
2793 | gk20a_init_vm(mm, vm, big_page_size, | 2753 | gk20a_init_vm(mm, vm, big_page_size, |
2794 | SZ_128K << 10, GK20A_PMU_VA_SIZE, false, "system"); | 2754 | SZ_128K << 10, GK20A_PMU_VA_SIZE, false, "system"); |
2795 | 2755 | ||
2796 | gk20a_dbg_info("pde pa=0x%llx", | ||
2797 | (u64)gk20a_mm_iova_addr(g, vm->pdes.sgt->sgl)); | ||
2798 | |||
2799 | pde_addr = gk20a_mm_iova_addr(g, vm->pdes.sgt->sgl); | ||
2800 | pde_addr_lo = u64_lo32(pde_addr >> ram_in_base_shift_v()); | ||
2801 | pde_addr_hi = u64_hi32(pde_addr); | ||
2802 | |||
2803 | err = gk20a_alloc_inst_block(g, inst_block); | 2756 | err = gk20a_alloc_inst_block(g, inst_block); |
2804 | if (err) | 2757 | if (err) |
2805 | goto clean_up_va; | 2758 | goto clean_up_va; |
2759 | gk20a_init_inst_block(inst_block, vm, big_page_size); | ||
2760 | |||
2761 | return 0; | ||
2762 | |||
2763 | clean_up_va: | ||
2764 | gk20a_deinit_vm(vm); | ||
2765 | return err; | ||
2766 | } | ||
2767 | |||
2768 | void gk20a_init_inst_block(struct inst_desc *inst_block, struct vm_gk20a *vm, | ||
2769 | u32 big_page_size) | ||
2770 | { | ||
2771 | struct gk20a *g = gk20a_from_vm(vm); | ||
2772 | u64 pde_addr = gk20a_mm_iova_addr(g, vm->pdes.sgt->sgl); | ||
2773 | u32 pde_addr_lo = u64_lo32(pde_addr >> ram_in_base_shift_v()); | ||
2774 | u32 pde_addr_hi = u64_hi32(pde_addr); | ||
2775 | phys_addr_t inst_pa = inst_block->cpu_pa; | ||
2776 | void *inst_ptr = inst_block->cpuva; | ||
2806 | 2777 | ||
2807 | inst_pa = inst_block->cpu_pa; | 2778 | gk20a_dbg_info("inst block phys = 0x%llx, kv = 0x%p", |
2808 | inst_ptr = inst_block->cpuva; | 2779 | (u64)inst_pa, inst_ptr); |
2809 | 2780 | ||
2810 | gk20a_dbg_info("pmu inst block physical addr: 0x%llx", (u64)inst_pa); | 2781 | gk20a_dbg_info("pde pa=0x%llx", (u64)pde_addr); |
2811 | 2782 | ||
2812 | gk20a_mem_wr32(inst_ptr, ram_in_page_dir_base_lo_w(), | 2783 | gk20a_mem_wr32(inst_ptr, ram_in_page_dir_base_lo_w(), |
2813 | ram_in_page_dir_base_target_vid_mem_f() | | 2784 | ram_in_page_dir_base_target_vid_mem_f() | |
@@ -2823,14 +2794,8 @@ static int gk20a_init_system_vm(struct mm_gk20a *mm) | |||
2823 | gk20a_mem_wr32(inst_ptr, ram_in_adr_limit_hi_w(), | 2794 | gk20a_mem_wr32(inst_ptr, ram_in_adr_limit_hi_w(), |
2824 | ram_in_adr_limit_hi_f(u64_hi32(vm->va_limit))); | 2795 | ram_in_adr_limit_hi_f(u64_hi32(vm->va_limit))); |
2825 | 2796 | ||
2826 | if (g->ops.mm.set_big_page_size) | 2797 | if (big_page_size && g->ops.mm.set_big_page_size) |
2827 | g->ops.mm.set_big_page_size(g, inst_ptr, big_page_size); | 2798 | g->ops.mm.set_big_page_size(g, inst_ptr, big_page_size); |
2828 | |||
2829 | return 0; | ||
2830 | |||
2831 | clean_up_va: | ||
2832 | gk20a_deinit_vm(vm); | ||
2833 | return err; | ||
2834 | } | 2799 | } |
2835 | 2800 | ||
2836 | int gk20a_mm_fb_flush(struct gk20a *g) | 2801 | int gk20a_mm_fb_flush(struct gk20a *g) |
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h index d39dcff0..79bc50af 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GK20A memory management | 2 | * GK20A memory management |
3 | * | 3 | * |
4 | * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2015, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -398,6 +398,8 @@ static inline int max_vaddr_bits_gk20a(void) | |||
398 | 398 | ||
399 | int gk20a_alloc_inst_block(struct gk20a *g, struct inst_desc *inst_block); | 399 | int gk20a_alloc_inst_block(struct gk20a *g, struct inst_desc *inst_block); |
400 | void gk20a_free_inst_block(struct gk20a *g, struct inst_desc *inst_block); | 400 | void gk20a_free_inst_block(struct gk20a *g, struct inst_desc *inst_block); |
401 | void gk20a_init_inst_block(struct inst_desc *inst_block, struct vm_gk20a *vm, | ||
402 | u32 big_page_size); | ||
401 | 403 | ||
402 | void gk20a_mm_dump_vm(struct vm_gk20a *vm, | 404 | void gk20a_mm_dump_vm(struct vm_gk20a *vm, |
403 | u64 va_begin, u64 va_end, char *label); | 405 | u64 va_begin, u64 va_end, char *label); |