diff options
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/regops_gm20b.c | 26 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/regops_gm20b.h | 14 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/regops_gp106.c | 24 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/regops_gp106.h | 14 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/regops_gp10b.c | 24 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/regops_gp10b.h | 14 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/regops_gv100.c | 24 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/regops_gv100.h | 14 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/regops_gv11b.c | 22 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/regops_gv11b.h | 14 |
11 files changed, 101 insertions, 101 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 5a888303..e51d768b 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -1124,20 +1124,20 @@ struct gpu_ops { | |||
1124 | u64 num_ops); | 1124 | u64 num_ops); |
1125 | const struct regop_offset_range* ( | 1125 | const struct regop_offset_range* ( |
1126 | *get_global_whitelist_ranges)(void); | 1126 | *get_global_whitelist_ranges)(void); |
1127 | int (*get_global_whitelist_ranges_count)(void); | 1127 | u64 (*get_global_whitelist_ranges_count)(void); |
1128 | const struct regop_offset_range* ( | 1128 | const struct regop_offset_range* ( |
1129 | *get_context_whitelist_ranges)(void); | 1129 | *get_context_whitelist_ranges)(void); |
1130 | int (*get_context_whitelist_ranges_count)(void); | 1130 | u64 (*get_context_whitelist_ranges_count)(void); |
1131 | const u32* (*get_runcontrol_whitelist)(void); | 1131 | const u32* (*get_runcontrol_whitelist)(void); |
1132 | int (*get_runcontrol_whitelist_count)(void); | 1132 | u64 (*get_runcontrol_whitelist_count)(void); |
1133 | const struct regop_offset_range* ( | 1133 | const struct regop_offset_range* ( |
1134 | *get_runcontrol_whitelist_ranges)(void); | 1134 | *get_runcontrol_whitelist_ranges)(void); |
1135 | int (*get_runcontrol_whitelist_ranges_count)(void); | 1135 | u64 (*get_runcontrol_whitelist_ranges_count)(void); |
1136 | const u32* (*get_qctl_whitelist)(void); | 1136 | const u32* (*get_qctl_whitelist)(void); |
1137 | int (*get_qctl_whitelist_count)(void); | 1137 | u64 (*get_qctl_whitelist_count)(void); |
1138 | const struct regop_offset_range* ( | 1138 | const struct regop_offset_range* ( |
1139 | *get_qctl_whitelist_ranges)(void); | 1139 | *get_qctl_whitelist_ranges)(void); |
1140 | int (*get_qctl_whitelist_ranges_count)(void); | 1140 | u64 (*get_qctl_whitelist_ranges_count)(void); |
1141 | int (*apply_smpc_war)(struct dbg_session_gk20a *dbg_s); | 1141 | int (*apply_smpc_war)(struct dbg_session_gk20a *dbg_s); |
1142 | } regops; | 1142 | } regops; |
1143 | struct { | 1143 | struct { |
diff --git a/drivers/gpu/nvgpu/gm20b/regops_gm20b.c b/drivers/gpu/nvgpu/gm20b/regops_gm20b.c index aaa055b6..e23a0a62 100644 --- a/drivers/gpu/nvgpu/gm20b/regops_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/regops_gm20b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Tegra GK20A GPU Debugger Driver Register Ops | 2 | * Tegra GK20A GPU Debugger Driver Register Ops |
3 | * | 3 | * |
4 | * Copyright (c) 2013-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2013-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -261,7 +261,7 @@ static const struct regop_offset_range gm20b_global_whitelist_ranges[] = { | |||
261 | { 0x00504eb0, 1 }, | 261 | { 0x00504eb0, 1 }, |
262 | { 0x00504ef0, 28 }, | 262 | { 0x00504ef0, 28 }, |
263 | }; | 263 | }; |
264 | static const u32 gm20b_global_whitelist_ranges_count = | 264 | static const u64 gm20b_global_whitelist_ranges_count = |
265 | ARRAY_SIZE(gm20b_global_whitelist_ranges); | 265 | ARRAY_SIZE(gm20b_global_whitelist_ranges); |
266 | 266 | ||
267 | /* context */ | 267 | /* context */ |
@@ -351,7 +351,7 @@ static const struct regop_offset_range gm20b_context_whitelist_ranges[] = { | |||
351 | { 0x00504ee8, 1 }, | 351 | { 0x00504ee8, 1 }, |
352 | { 0x00504ef0, 28 }, | 352 | { 0x00504ef0, 28 }, |
353 | }; | 353 | }; |
354 | static const u32 gm20b_context_whitelist_ranges_count = | 354 | static const u64 gm20b_context_whitelist_ranges_count = |
355 | ARRAY_SIZE(gm20b_context_whitelist_ranges); | 355 | ARRAY_SIZE(gm20b_context_whitelist_ranges); |
356 | 356 | ||
357 | /* runcontrol */ | 357 | /* runcontrol */ |
@@ -363,7 +363,7 @@ static const u32 gm20b_runcontrol_whitelist[] = { | |||
363 | 0x00504610, | 363 | 0x00504610, |
364 | 0x00504e10, | 364 | 0x00504e10, |
365 | }; | 365 | }; |
366 | static const u32 gm20b_runcontrol_whitelist_count = | 366 | static const u64 gm20b_runcontrol_whitelist_count = |
367 | ARRAY_SIZE(gm20b_runcontrol_whitelist); | 367 | ARRAY_SIZE(gm20b_runcontrol_whitelist); |
368 | 368 | ||
369 | static const struct regop_offset_range gm20b_runcontrol_whitelist_ranges[] = { | 369 | static const struct regop_offset_range gm20b_runcontrol_whitelist_ranges[] = { |
@@ -374,19 +374,19 @@ static const struct regop_offset_range gm20b_runcontrol_whitelist_ranges[] = { | |||
374 | { 0x00504610, 1 }, | 374 | { 0x00504610, 1 }, |
375 | { 0x00504e10, 1 }, | 375 | { 0x00504e10, 1 }, |
376 | }; | 376 | }; |
377 | static const u32 gm20b_runcontrol_whitelist_ranges_count = | 377 | static const u64 gm20b_runcontrol_whitelist_ranges_count = |
378 | ARRAY_SIZE(gm20b_runcontrol_whitelist_ranges); | 378 | ARRAY_SIZE(gm20b_runcontrol_whitelist_ranges); |
379 | 379 | ||
380 | 380 | ||
381 | /* quad ctl */ | 381 | /* quad ctl */ |
382 | static const u32 gm20b_qctl_whitelist[] = { | 382 | static const u32 gm20b_qctl_whitelist[] = { |
383 | }; | 383 | }; |
384 | static const u32 gm20b_qctl_whitelist_count = | 384 | static const u64 gm20b_qctl_whitelist_count = |
385 | ARRAY_SIZE(gm20b_qctl_whitelist); | 385 | ARRAY_SIZE(gm20b_qctl_whitelist); |
386 | 386 | ||
387 | static const struct regop_offset_range gm20b_qctl_whitelist_ranges[] = { | 387 | static const struct regop_offset_range gm20b_qctl_whitelist_ranges[] = { |
388 | }; | 388 | }; |
389 | static const u32 gm20b_qctl_whitelist_ranges_count = | 389 | static const u64 gm20b_qctl_whitelist_ranges_count = |
390 | ARRAY_SIZE(gm20b_qctl_whitelist_ranges); | 390 | ARRAY_SIZE(gm20b_qctl_whitelist_ranges); |
391 | 391 | ||
392 | const struct regop_offset_range *gm20b_get_global_whitelist_ranges(void) | 392 | const struct regop_offset_range *gm20b_get_global_whitelist_ranges(void) |
@@ -394,7 +394,7 @@ const struct regop_offset_range *gm20b_get_global_whitelist_ranges(void) | |||
394 | return gm20b_global_whitelist_ranges; | 394 | return gm20b_global_whitelist_ranges; |
395 | } | 395 | } |
396 | 396 | ||
397 | int gm20b_get_global_whitelist_ranges_count(void) | 397 | u64 gm20b_get_global_whitelist_ranges_count(void) |
398 | { | 398 | { |
399 | return gm20b_global_whitelist_ranges_count; | 399 | return gm20b_global_whitelist_ranges_count; |
400 | } | 400 | } |
@@ -404,7 +404,7 @@ const struct regop_offset_range *gm20b_get_context_whitelist_ranges(void) | |||
404 | return gm20b_context_whitelist_ranges; | 404 | return gm20b_context_whitelist_ranges; |
405 | } | 405 | } |
406 | 406 | ||
407 | int gm20b_get_context_whitelist_ranges_count(void) | 407 | u64 gm20b_get_context_whitelist_ranges_count(void) |
408 | { | 408 | { |
409 | return gm20b_context_whitelist_ranges_count; | 409 | return gm20b_context_whitelist_ranges_count; |
410 | } | 410 | } |
@@ -414,7 +414,7 @@ const u32 *gm20b_get_runcontrol_whitelist(void) | |||
414 | return gm20b_runcontrol_whitelist; | 414 | return gm20b_runcontrol_whitelist; |
415 | } | 415 | } |
416 | 416 | ||
417 | int gm20b_get_runcontrol_whitelist_count(void) | 417 | u64 gm20b_get_runcontrol_whitelist_count(void) |
418 | { | 418 | { |
419 | return gm20b_runcontrol_whitelist_count; | 419 | return gm20b_runcontrol_whitelist_count; |
420 | } | 420 | } |
@@ -424,7 +424,7 @@ const struct regop_offset_range *gm20b_get_runcontrol_whitelist_ranges(void) | |||
424 | return gm20b_runcontrol_whitelist_ranges; | 424 | return gm20b_runcontrol_whitelist_ranges; |
425 | } | 425 | } |
426 | 426 | ||
427 | int gm20b_get_runcontrol_whitelist_ranges_count(void) | 427 | u64 gm20b_get_runcontrol_whitelist_ranges_count(void) |
428 | { | 428 | { |
429 | return gm20b_runcontrol_whitelist_ranges_count; | 429 | return gm20b_runcontrol_whitelist_ranges_count; |
430 | } | 430 | } |
@@ -434,7 +434,7 @@ const u32 *gm20b_get_qctl_whitelist(void) | |||
434 | return gm20b_qctl_whitelist; | 434 | return gm20b_qctl_whitelist; |
435 | } | 435 | } |
436 | 436 | ||
437 | int gm20b_get_qctl_whitelist_count(void) | 437 | u64 gm20b_get_qctl_whitelist_count(void) |
438 | { | 438 | { |
439 | return gm20b_qctl_whitelist_count; | 439 | return gm20b_qctl_whitelist_count; |
440 | } | 440 | } |
@@ -444,7 +444,7 @@ const struct regop_offset_range *gm20b_get_qctl_whitelist_ranges(void) | |||
444 | return gm20b_qctl_whitelist_ranges; | 444 | return gm20b_qctl_whitelist_ranges; |
445 | } | 445 | } |
446 | 446 | ||
447 | int gm20b_get_qctl_whitelist_ranges_count(void) | 447 | u64 gm20b_get_qctl_whitelist_ranges_count(void) |
448 | { | 448 | { |
449 | return gm20b_qctl_whitelist_ranges_count; | 449 | return gm20b_qctl_whitelist_ranges_count; |
450 | } | 450 | } |
diff --git a/drivers/gpu/nvgpu/gm20b/regops_gm20b.h b/drivers/gpu/nvgpu/gm20b/regops_gm20b.h index f0246e0e..99044f09 100644 --- a/drivers/gpu/nvgpu/gm20b/regops_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/regops_gm20b.h | |||
@@ -2,7 +2,7 @@ | |||
2 | * | 2 | * |
3 | * Tegra GK20A GPU Debugger Driver Register Ops | 3 | * Tegra GK20A GPU Debugger Driver Register Ops |
4 | * | 4 | * |
5 | * Copyright (c) 2013-2017, NVIDIA CORPORATION. All rights reserved. | 5 | * Copyright (c) 2013-2018 NVIDIA CORPORATION. All rights reserved. |
6 | * | 6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | 7 | * Permission is hereby granted, free of charge, to any person obtaining a |
8 | * copy of this software and associated documentation files (the "Software"), | 8 | * copy of this software and associated documentation files (the "Software"), |
@@ -28,17 +28,17 @@ | |||
28 | struct dbg_session_gk20a; | 28 | struct dbg_session_gk20a; |
29 | 29 | ||
30 | const struct regop_offset_range *gm20b_get_global_whitelist_ranges(void); | 30 | const struct regop_offset_range *gm20b_get_global_whitelist_ranges(void); |
31 | int gm20b_get_global_whitelist_ranges_count(void); | 31 | u64 gm20b_get_global_whitelist_ranges_count(void); |
32 | const struct regop_offset_range *gm20b_get_context_whitelist_ranges(void); | 32 | const struct regop_offset_range *gm20b_get_context_whitelist_ranges(void); |
33 | int gm20b_get_context_whitelist_ranges_count(void); | 33 | u64 gm20b_get_context_whitelist_ranges_count(void); |
34 | const u32 *gm20b_get_runcontrol_whitelist(void); | 34 | const u32 *gm20b_get_runcontrol_whitelist(void); |
35 | int gm20b_get_runcontrol_whitelist_count(void); | 35 | u64 gm20b_get_runcontrol_whitelist_count(void); |
36 | const struct regop_offset_range *gm20b_get_runcontrol_whitelist_ranges(void); | 36 | const struct regop_offset_range *gm20b_get_runcontrol_whitelist_ranges(void); |
37 | int gm20b_get_runcontrol_whitelist_ranges_count(void); | 37 | u64 gm20b_get_runcontrol_whitelist_ranges_count(void); |
38 | const u32 *gm20b_get_qctl_whitelist(void); | 38 | const u32 *gm20b_get_qctl_whitelist(void); |
39 | int gm20b_get_qctl_whitelist_count(void); | 39 | u64 gm20b_get_qctl_whitelist_count(void); |
40 | const struct regop_offset_range *gm20b_get_qctl_whitelist_ranges(void); | 40 | const struct regop_offset_range *gm20b_get_qctl_whitelist_ranges(void); |
41 | int gm20b_get_qctl_whitelist_ranges_count(void); | 41 | u64 gm20b_get_qctl_whitelist_ranges_count(void); |
42 | int gm20b_apply_smpc_war(struct dbg_session_gk20a *dbg_s); | 42 | int gm20b_apply_smpc_war(struct dbg_session_gk20a *dbg_s); |
43 | 43 | ||
44 | #endif /* __REGOPS_GM20B_H_ */ | 44 | #endif /* __REGOPS_GM20B_H_ */ |
diff --git a/drivers/gpu/nvgpu/gp106/regops_gp106.c b/drivers/gpu/nvgpu/gp106/regops_gp106.c index d9dadbac..25b88eeb 100644 --- a/drivers/gpu/nvgpu/gp106/regops_gp106.c +++ b/drivers/gpu/nvgpu/gp106/regops_gp106.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Tegra GP106 GPU Debugger Driver Register Ops | 2 | * Tegra GP106 GPU Debugger Driver Register Ops |
3 | * | 3 | * |
4 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -1686,7 +1686,7 @@ static const struct regop_offset_range gp106_global_whitelist_ranges[] = { | |||
1686 | }; | 1686 | }; |
1687 | 1687 | ||
1688 | 1688 | ||
1689 | static const u32 gp106_global_whitelist_ranges_count = | 1689 | static const u64 gp106_global_whitelist_ranges_count = |
1690 | ARRAY_SIZE(gp106_global_whitelist_ranges); | 1690 | ARRAY_SIZE(gp106_global_whitelist_ranges); |
1691 | 1691 | ||
1692 | /* context */ | 1692 | /* context */ |
@@ -1694,24 +1694,24 @@ static const u32 gp106_global_whitelist_ranges_count = | |||
1694 | /* runcontrol */ | 1694 | /* runcontrol */ |
1695 | static const u32 gp106_runcontrol_whitelist[] = { | 1695 | static const u32 gp106_runcontrol_whitelist[] = { |
1696 | }; | 1696 | }; |
1697 | static const u32 gp106_runcontrol_whitelist_count = | 1697 | static const u64 gp106_runcontrol_whitelist_count = |
1698 | ARRAY_SIZE(gp106_runcontrol_whitelist); | 1698 | ARRAY_SIZE(gp106_runcontrol_whitelist); |
1699 | 1699 | ||
1700 | static const struct regop_offset_range gp106_runcontrol_whitelist_ranges[] = { | 1700 | static const struct regop_offset_range gp106_runcontrol_whitelist_ranges[] = { |
1701 | }; | 1701 | }; |
1702 | static const u32 gp106_runcontrol_whitelist_ranges_count = | 1702 | static const u64 gp106_runcontrol_whitelist_ranges_count = |
1703 | ARRAY_SIZE(gp106_runcontrol_whitelist_ranges); | 1703 | ARRAY_SIZE(gp106_runcontrol_whitelist_ranges); |
1704 | 1704 | ||
1705 | 1705 | ||
1706 | /* quad ctl */ | 1706 | /* quad ctl */ |
1707 | static const u32 gp106_qctl_whitelist[] = { | 1707 | static const u32 gp106_qctl_whitelist[] = { |
1708 | }; | 1708 | }; |
1709 | static const u32 gp106_qctl_whitelist_count = | 1709 | static const u64 gp106_qctl_whitelist_count = |
1710 | ARRAY_SIZE(gp106_qctl_whitelist); | 1710 | ARRAY_SIZE(gp106_qctl_whitelist); |
1711 | 1711 | ||
1712 | static const struct regop_offset_range gp106_qctl_whitelist_ranges[] = { | 1712 | static const struct regop_offset_range gp106_qctl_whitelist_ranges[] = { |
1713 | }; | 1713 | }; |
1714 | static const u32 gp106_qctl_whitelist_ranges_count = | 1714 | static const u64 gp106_qctl_whitelist_ranges_count = |
1715 | ARRAY_SIZE(gp106_qctl_whitelist_ranges); | 1715 | ARRAY_SIZE(gp106_qctl_whitelist_ranges); |
1716 | 1716 | ||
1717 | const struct regop_offset_range *gp106_get_global_whitelist_ranges(void) | 1717 | const struct regop_offset_range *gp106_get_global_whitelist_ranges(void) |
@@ -1719,7 +1719,7 @@ const struct regop_offset_range *gp106_get_global_whitelist_ranges(void) | |||
1719 | return gp106_global_whitelist_ranges; | 1719 | return gp106_global_whitelist_ranges; |
1720 | } | 1720 | } |
1721 | 1721 | ||
1722 | int gp106_get_global_whitelist_ranges_count(void) | 1722 | u64 gp106_get_global_whitelist_ranges_count(void) |
1723 | { | 1723 | { |
1724 | return gp106_global_whitelist_ranges_count; | 1724 | return gp106_global_whitelist_ranges_count; |
1725 | } | 1725 | } |
@@ -1729,7 +1729,7 @@ const struct regop_offset_range *gp106_get_context_whitelist_ranges(void) | |||
1729 | return gp106_global_whitelist_ranges; | 1729 | return gp106_global_whitelist_ranges; |
1730 | } | 1730 | } |
1731 | 1731 | ||
1732 | int gp106_get_context_whitelist_ranges_count(void) | 1732 | u64 gp106_get_context_whitelist_ranges_count(void) |
1733 | { | 1733 | { |
1734 | return gp106_global_whitelist_ranges_count; | 1734 | return gp106_global_whitelist_ranges_count; |
1735 | } | 1735 | } |
@@ -1739,7 +1739,7 @@ const u32 *gp106_get_runcontrol_whitelist(void) | |||
1739 | return gp106_runcontrol_whitelist; | 1739 | return gp106_runcontrol_whitelist; |
1740 | } | 1740 | } |
1741 | 1741 | ||
1742 | int gp106_get_runcontrol_whitelist_count(void) | 1742 | u64 gp106_get_runcontrol_whitelist_count(void) |
1743 | { | 1743 | { |
1744 | return gp106_runcontrol_whitelist_count; | 1744 | return gp106_runcontrol_whitelist_count; |
1745 | } | 1745 | } |
@@ -1749,7 +1749,7 @@ const struct regop_offset_range *gp106_get_runcontrol_whitelist_ranges(void) | |||
1749 | return gp106_runcontrol_whitelist_ranges; | 1749 | return gp106_runcontrol_whitelist_ranges; |
1750 | } | 1750 | } |
1751 | 1751 | ||
1752 | int gp106_get_runcontrol_whitelist_ranges_count(void) | 1752 | u64 gp106_get_runcontrol_whitelist_ranges_count(void) |
1753 | { | 1753 | { |
1754 | return gp106_runcontrol_whitelist_ranges_count; | 1754 | return gp106_runcontrol_whitelist_ranges_count; |
1755 | } | 1755 | } |
@@ -1759,7 +1759,7 @@ const u32 *gp106_get_qctl_whitelist(void) | |||
1759 | return gp106_qctl_whitelist; | 1759 | return gp106_qctl_whitelist; |
1760 | } | 1760 | } |
1761 | 1761 | ||
1762 | int gp106_get_qctl_whitelist_count(void) | 1762 | u64 gp106_get_qctl_whitelist_count(void) |
1763 | { | 1763 | { |
1764 | return gp106_qctl_whitelist_count; | 1764 | return gp106_qctl_whitelist_count; |
1765 | } | 1765 | } |
@@ -1769,7 +1769,7 @@ const struct regop_offset_range *gp106_get_qctl_whitelist_ranges(void) | |||
1769 | return gp106_qctl_whitelist_ranges; | 1769 | return gp106_qctl_whitelist_ranges; |
1770 | } | 1770 | } |
1771 | 1771 | ||
1772 | int gp106_get_qctl_whitelist_ranges_count(void) | 1772 | u64 gp106_get_qctl_whitelist_ranges_count(void) |
1773 | { | 1773 | { |
1774 | return gp106_qctl_whitelist_ranges_count; | 1774 | return gp106_qctl_whitelist_ranges_count; |
1775 | } | 1775 | } |
diff --git a/drivers/gpu/nvgpu/gp106/regops_gp106.h b/drivers/gpu/nvgpu/gp106/regops_gp106.h index 801e6f1c..45f1fb49 100644 --- a/drivers/gpu/nvgpu/gp106/regops_gp106.h +++ b/drivers/gpu/nvgpu/gp106/regops_gp106.h | |||
@@ -2,7 +2,7 @@ | |||
2 | * | 2 | * |
3 | * Tegra GP106 GPU Debugger Driver Register Ops | 3 | * Tegra GP106 GPU Debugger Driver Register Ops |
4 | * | 4 | * |
5 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 5 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
6 | * | 6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | 7 | * Permission is hereby granted, free of charge, to any person obtaining a |
8 | * copy of this software and associated documentation files (the "Software"), | 8 | * copy of this software and associated documentation files (the "Software"), |
@@ -26,17 +26,17 @@ | |||
26 | #define __REGOPS_GP106_H_ | 26 | #define __REGOPS_GP106_H_ |
27 | 27 | ||
28 | const struct regop_offset_range *gp106_get_global_whitelist_ranges(void); | 28 | const struct regop_offset_range *gp106_get_global_whitelist_ranges(void); |
29 | int gp106_get_global_whitelist_ranges_count(void); | 29 | u64 gp106_get_global_whitelist_ranges_count(void); |
30 | const struct regop_offset_range *gp106_get_context_whitelist_ranges(void); | 30 | const struct regop_offset_range *gp106_get_context_whitelist_ranges(void); |
31 | int gp106_get_context_whitelist_ranges_count(void); | 31 | u64 gp106_get_context_whitelist_ranges_count(void); |
32 | const u32 *gp106_get_runcontrol_whitelist(void); | 32 | const u32 *gp106_get_runcontrol_whitelist(void); |
33 | int gp106_get_runcontrol_whitelist_count(void); | 33 | u64 gp106_get_runcontrol_whitelist_count(void); |
34 | const struct regop_offset_range *gp106_get_runcontrol_whitelist_ranges(void); | 34 | const struct regop_offset_range *gp106_get_runcontrol_whitelist_ranges(void); |
35 | int gp106_get_runcontrol_whitelist_ranges_count(void); | 35 | u64 gp106_get_runcontrol_whitelist_ranges_count(void); |
36 | const u32 *gp106_get_qctl_whitelist(void); | 36 | const u32 *gp106_get_qctl_whitelist(void); |
37 | int gp106_get_qctl_whitelist_count(void); | 37 | u64 gp106_get_qctl_whitelist_count(void); |
38 | const struct regop_offset_range *gp106_get_qctl_whitelist_ranges(void); | 38 | const struct regop_offset_range *gp106_get_qctl_whitelist_ranges(void); |
39 | int gp106_get_qctl_whitelist_ranges_count(void); | 39 | u64 gp106_get_qctl_whitelist_ranges_count(void); |
40 | int gp106_apply_smpc_war(struct dbg_session_gk20a *dbg_s); | 40 | int gp106_apply_smpc_war(struct dbg_session_gk20a *dbg_s); |
41 | 41 | ||
42 | #endif /* __REGOPS_GP106_H_ */ | 42 | #endif /* __REGOPS_GP106_H_ */ |
diff --git a/drivers/gpu/nvgpu/gp10b/regops_gp10b.c b/drivers/gpu/nvgpu/gp10b/regops_gp10b.c index 60f36b6c..8113f7d5 100644 --- a/drivers/gpu/nvgpu/gp10b/regops_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/regops_gp10b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Tegra GK20A GPU Debugger Driver Register Ops | 2 | * Tegra GK20A GPU Debugger Driver Register Ops |
3 | * | 3 | * |
4 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -382,7 +382,7 @@ static const struct regop_offset_range gp10b_global_whitelist_ranges[] = { | |||
382 | { 0x009a0100, 1}, | 382 | { 0x009a0100, 1}, |
383 | }; | 383 | }; |
384 | 384 | ||
385 | static const u32 gp10b_global_whitelist_ranges_count = | 385 | static const u64 gp10b_global_whitelist_ranges_count = |
386 | ARRAY_SIZE(gp10b_global_whitelist_ranges); | 386 | ARRAY_SIZE(gp10b_global_whitelist_ranges); |
387 | 387 | ||
388 | /* context */ | 388 | /* context */ |
@@ -390,24 +390,24 @@ static const u32 gp10b_global_whitelist_ranges_count = | |||
390 | /* runcontrol */ | 390 | /* runcontrol */ |
391 | static const u32 gp10b_runcontrol_whitelist[] = { | 391 | static const u32 gp10b_runcontrol_whitelist[] = { |
392 | }; | 392 | }; |
393 | static const u32 gp10b_runcontrol_whitelist_count = | 393 | static const u64 gp10b_runcontrol_whitelist_count = |
394 | ARRAY_SIZE(gp10b_runcontrol_whitelist); | 394 | ARRAY_SIZE(gp10b_runcontrol_whitelist); |
395 | 395 | ||
396 | static const struct regop_offset_range gp10b_runcontrol_whitelist_ranges[] = { | 396 | static const struct regop_offset_range gp10b_runcontrol_whitelist_ranges[] = { |
397 | }; | 397 | }; |
398 | static const u32 gp10b_runcontrol_whitelist_ranges_count = | 398 | static const u64 gp10b_runcontrol_whitelist_ranges_count = |
399 | ARRAY_SIZE(gp10b_runcontrol_whitelist_ranges); | 399 | ARRAY_SIZE(gp10b_runcontrol_whitelist_ranges); |
400 | 400 | ||
401 | 401 | ||
402 | /* quad ctl */ | 402 | /* quad ctl */ |
403 | static const u32 gp10b_qctl_whitelist[] = { | 403 | static const u32 gp10b_qctl_whitelist[] = { |
404 | }; | 404 | }; |
405 | static const u32 gp10b_qctl_whitelist_count = | 405 | static const u64 gp10b_qctl_whitelist_count = |
406 | ARRAY_SIZE(gp10b_qctl_whitelist); | 406 | ARRAY_SIZE(gp10b_qctl_whitelist); |
407 | 407 | ||
408 | static const struct regop_offset_range gp10b_qctl_whitelist_ranges[] = { | 408 | static const struct regop_offset_range gp10b_qctl_whitelist_ranges[] = { |
409 | }; | 409 | }; |
410 | static const u32 gp10b_qctl_whitelist_ranges_count = | 410 | static const u64 gp10b_qctl_whitelist_ranges_count = |
411 | ARRAY_SIZE(gp10b_qctl_whitelist_ranges); | 411 | ARRAY_SIZE(gp10b_qctl_whitelist_ranges); |
412 | 412 | ||
413 | const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void) | 413 | const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void) |
@@ -415,7 +415,7 @@ const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void) | |||
415 | return gp10b_global_whitelist_ranges; | 415 | return gp10b_global_whitelist_ranges; |
416 | } | 416 | } |
417 | 417 | ||
418 | int gp10b_get_global_whitelist_ranges_count(void) | 418 | u64 gp10b_get_global_whitelist_ranges_count(void) |
419 | { | 419 | { |
420 | return gp10b_global_whitelist_ranges_count; | 420 | return gp10b_global_whitelist_ranges_count; |
421 | } | 421 | } |
@@ -425,7 +425,7 @@ const struct regop_offset_range *gp10b_get_context_whitelist_ranges(void) | |||
425 | return gp10b_global_whitelist_ranges; | 425 | return gp10b_global_whitelist_ranges; |
426 | } | 426 | } |
427 | 427 | ||
428 | int gp10b_get_context_whitelist_ranges_count(void) | 428 | u64 gp10b_get_context_whitelist_ranges_count(void) |
429 | { | 429 | { |
430 | return gp10b_global_whitelist_ranges_count; | 430 | return gp10b_global_whitelist_ranges_count; |
431 | } | 431 | } |
@@ -435,7 +435,7 @@ const u32 *gp10b_get_runcontrol_whitelist(void) | |||
435 | return gp10b_runcontrol_whitelist; | 435 | return gp10b_runcontrol_whitelist; |
436 | } | 436 | } |
437 | 437 | ||
438 | int gp10b_get_runcontrol_whitelist_count(void) | 438 | u64 gp10b_get_runcontrol_whitelist_count(void) |
439 | { | 439 | { |
440 | return gp10b_runcontrol_whitelist_count; | 440 | return gp10b_runcontrol_whitelist_count; |
441 | } | 441 | } |
@@ -445,7 +445,7 @@ const struct regop_offset_range *gp10b_get_runcontrol_whitelist_ranges(void) | |||
445 | return gp10b_runcontrol_whitelist_ranges; | 445 | return gp10b_runcontrol_whitelist_ranges; |
446 | } | 446 | } |
447 | 447 | ||
448 | int gp10b_get_runcontrol_whitelist_ranges_count(void) | 448 | u64 gp10b_get_runcontrol_whitelist_ranges_count(void) |
449 | { | 449 | { |
450 | return gp10b_runcontrol_whitelist_ranges_count; | 450 | return gp10b_runcontrol_whitelist_ranges_count; |
451 | } | 451 | } |
@@ -455,7 +455,7 @@ const u32 *gp10b_get_qctl_whitelist(void) | |||
455 | return gp10b_qctl_whitelist; | 455 | return gp10b_qctl_whitelist; |
456 | } | 456 | } |
457 | 457 | ||
458 | int gp10b_get_qctl_whitelist_count(void) | 458 | u64 gp10b_get_qctl_whitelist_count(void) |
459 | { | 459 | { |
460 | return gp10b_qctl_whitelist_count; | 460 | return gp10b_qctl_whitelist_count; |
461 | } | 461 | } |
@@ -465,7 +465,7 @@ const struct regop_offset_range *gp10b_get_qctl_whitelist_ranges(void) | |||
465 | return gp10b_qctl_whitelist_ranges; | 465 | return gp10b_qctl_whitelist_ranges; |
466 | } | 466 | } |
467 | 467 | ||
468 | int gp10b_get_qctl_whitelist_ranges_count(void) | 468 | u64 gp10b_get_qctl_whitelist_ranges_count(void) |
469 | { | 469 | { |
470 | return gp10b_qctl_whitelist_ranges_count; | 470 | return gp10b_qctl_whitelist_ranges_count; |
471 | } | 471 | } |
diff --git a/drivers/gpu/nvgpu/gp10b/regops_gp10b.h b/drivers/gpu/nvgpu/gp10b/regops_gp10b.h index 7bc08189..e8b9f325 100644 --- a/drivers/gpu/nvgpu/gp10b/regops_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/regops_gp10b.h | |||
@@ -2,7 +2,7 @@ | |||
2 | * | 2 | * |
3 | * Tegra GP10B GPU Debugger Driver Register Ops | 3 | * Tegra GP10B GPU Debugger Driver Register Ops |
4 | * | 4 | * |
5 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. | 5 | * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. |
6 | * | 6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | 7 | * Permission is hereby granted, free of charge, to any person obtaining a |
8 | * copy of this software and associated documentation files (the "Software"), | 8 | * copy of this software and associated documentation files (the "Software"), |
@@ -28,17 +28,17 @@ | |||
28 | struct dbg_session_gk20a; | 28 | struct dbg_session_gk20a; |
29 | 29 | ||
30 | const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void); | 30 | const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void); |
31 | int gp10b_get_global_whitelist_ranges_count(void); | 31 | u64 gp10b_get_global_whitelist_ranges_count(void); |
32 | const struct regop_offset_range *gp10b_get_context_whitelist_ranges(void); | 32 | const struct regop_offset_range *gp10b_get_context_whitelist_ranges(void); |
33 | int gp10b_get_context_whitelist_ranges_count(void); | 33 | u64 gp10b_get_context_whitelist_ranges_count(void); |
34 | const u32 *gp10b_get_runcontrol_whitelist(void); | 34 | const u32 *gp10b_get_runcontrol_whitelist(void); |
35 | int gp10b_get_runcontrol_whitelist_count(void); | 35 | u64 gp10b_get_runcontrol_whitelist_count(void); |
36 | const struct regop_offset_range *gp10b_get_runcontrol_whitelist_ranges(void); | 36 | const struct regop_offset_range *gp10b_get_runcontrol_whitelist_ranges(void); |
37 | int gp10b_get_runcontrol_whitelist_ranges_count(void); | 37 | u64 gp10b_get_runcontrol_whitelist_ranges_count(void); |
38 | const u32 *gp10b_get_qctl_whitelist(void); | 38 | const u32 *gp10b_get_qctl_whitelist(void); |
39 | int gp10b_get_qctl_whitelist_count(void); | 39 | u64 gp10b_get_qctl_whitelist_count(void); |
40 | const struct regop_offset_range *gp10b_get_qctl_whitelist_ranges(void); | 40 | const struct regop_offset_range *gp10b_get_qctl_whitelist_ranges(void); |
41 | int gp10b_get_qctl_whitelist_ranges_count(void); | 41 | u64 gp10b_get_qctl_whitelist_ranges_count(void); |
42 | int gp10b_apply_smpc_war(struct dbg_session_gk20a *dbg_s); | 42 | int gp10b_apply_smpc_war(struct dbg_session_gk20a *dbg_s); |
43 | 43 | ||
44 | #endif /* __REGOPS_GP10B_H_ */ | 44 | #endif /* __REGOPS_GP10B_H_ */ |
diff --git a/drivers/gpu/nvgpu/gv100/regops_gv100.c b/drivers/gpu/nvgpu/gv100/regops_gv100.c index 857fc01d..c6ce6b94 100644 --- a/drivers/gpu/nvgpu/gv100/regops_gv100.c +++ b/drivers/gpu/nvgpu/gv100/regops_gv100.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Tegra GV100 GPU Driver Register Ops | 2 | * Tegra GV100 GPU Driver Register Ops |
3 | * | 3 | * |
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -5623,7 +5623,7 @@ static const struct regop_offset_range gv100_global_whitelist_ranges[] = { | |||
5623 | { 0x00a3eed4, 7}, | 5623 | { 0x00a3eed4, 7}, |
5624 | { 0x00a3eef4, 2}}; | 5624 | { 0x00a3eef4, 2}}; |
5625 | 5625 | ||
5626 | static const u32 gv100_global_whitelist_ranges_count = | 5626 | static const u64 gv100_global_whitelist_ranges_count = |
5627 | ARRAY_SIZE(gv100_global_whitelist_ranges); | 5627 | ARRAY_SIZE(gv100_global_whitelist_ranges); |
5628 | 5628 | ||
5629 | /* context */ | 5629 | /* context */ |
@@ -5631,24 +5631,24 @@ static const u32 gv100_global_whitelist_ranges_count = | |||
5631 | /* runcontrol */ | 5631 | /* runcontrol */ |
5632 | static const u32 gv100_runcontrol_whitelist[] = { | 5632 | static const u32 gv100_runcontrol_whitelist[] = { |
5633 | }; | 5633 | }; |
5634 | static const u32 gv100_runcontrol_whitelist_count = | 5634 | static const u64 gv100_runcontrol_whitelist_count = |
5635 | ARRAY_SIZE(gv100_runcontrol_whitelist); | 5635 | ARRAY_SIZE(gv100_runcontrol_whitelist); |
5636 | 5636 | ||
5637 | static const struct regop_offset_range gv100_runcontrol_whitelist_ranges[] = { | 5637 | static const struct regop_offset_range gv100_runcontrol_whitelist_ranges[] = { |
5638 | }; | 5638 | }; |
5639 | static const u32 gv100_runcontrol_whitelist_ranges_count = | 5639 | static const u64 gv100_runcontrol_whitelist_ranges_count = |
5640 | ARRAY_SIZE(gv100_runcontrol_whitelist_ranges); | 5640 | ARRAY_SIZE(gv100_runcontrol_whitelist_ranges); |
5641 | 5641 | ||
5642 | 5642 | ||
5643 | /* quad ctl */ | 5643 | /* quad ctl */ |
5644 | static const u32 gv100_qctl_whitelist[] = { | 5644 | static const u32 gv100_qctl_whitelist[] = { |
5645 | }; | 5645 | }; |
5646 | static const u32 gv100_qctl_whitelist_count = | 5646 | static const u64 gv100_qctl_whitelist_count = |
5647 | ARRAY_SIZE(gv100_qctl_whitelist); | 5647 | ARRAY_SIZE(gv100_qctl_whitelist); |
5648 | 5648 | ||
5649 | static const struct regop_offset_range gv100_qctl_whitelist_ranges[] = { | 5649 | static const struct regop_offset_range gv100_qctl_whitelist_ranges[] = { |
5650 | }; | 5650 | }; |
5651 | static const u32 gv100_qctl_whitelist_ranges_count = | 5651 | static const u64 gv100_qctl_whitelist_ranges_count = |
5652 | ARRAY_SIZE(gv100_qctl_whitelist_ranges); | 5652 | ARRAY_SIZE(gv100_qctl_whitelist_ranges); |
5653 | 5653 | ||
5654 | const struct regop_offset_range *gv100_get_global_whitelist_ranges(void) | 5654 | const struct regop_offset_range *gv100_get_global_whitelist_ranges(void) |
@@ -5656,7 +5656,7 @@ const struct regop_offset_range *gv100_get_global_whitelist_ranges(void) | |||
5656 | return gv100_global_whitelist_ranges; | 5656 | return gv100_global_whitelist_ranges; |
5657 | } | 5657 | } |
5658 | 5658 | ||
5659 | int gv100_get_global_whitelist_ranges_count(void) | 5659 | u64 gv100_get_global_whitelist_ranges_count(void) |
5660 | { | 5660 | { |
5661 | return gv100_global_whitelist_ranges_count; | 5661 | return gv100_global_whitelist_ranges_count; |
5662 | } | 5662 | } |
@@ -5666,7 +5666,7 @@ const struct regop_offset_range *gv100_get_context_whitelist_ranges(void) | |||
5666 | return gv100_global_whitelist_ranges; | 5666 | return gv100_global_whitelist_ranges; |
5667 | } | 5667 | } |
5668 | 5668 | ||
5669 | int gv100_get_context_whitelist_ranges_count(void) | 5669 | u64 gv100_get_context_whitelist_ranges_count(void) |
5670 | { | 5670 | { |
5671 | return gv100_global_whitelist_ranges_count; | 5671 | return gv100_global_whitelist_ranges_count; |
5672 | } | 5672 | } |
@@ -5676,7 +5676,7 @@ const u32 *gv100_get_runcontrol_whitelist(void) | |||
5676 | return gv100_runcontrol_whitelist; | 5676 | return gv100_runcontrol_whitelist; |
5677 | } | 5677 | } |
5678 | 5678 | ||
5679 | int gv100_get_runcontrol_whitelist_count(void) | 5679 | u64 gv100_get_runcontrol_whitelist_count(void) |
5680 | { | 5680 | { |
5681 | return gv100_runcontrol_whitelist_count; | 5681 | return gv100_runcontrol_whitelist_count; |
5682 | } | 5682 | } |
@@ -5686,7 +5686,7 @@ const struct regop_offset_range *gv100_get_runcontrol_whitelist_ranges(void) | |||
5686 | return gv100_runcontrol_whitelist_ranges; | 5686 | return gv100_runcontrol_whitelist_ranges; |
5687 | } | 5687 | } |
5688 | 5688 | ||
5689 | int gv100_get_runcontrol_whitelist_ranges_count(void) | 5689 | u64 gv100_get_runcontrol_whitelist_ranges_count(void) |
5690 | { | 5690 | { |
5691 | return gv100_runcontrol_whitelist_ranges_count; | 5691 | return gv100_runcontrol_whitelist_ranges_count; |
5692 | } | 5692 | } |
@@ -5696,7 +5696,7 @@ const u32 *gv100_get_qctl_whitelist(void) | |||
5696 | return gv100_qctl_whitelist; | 5696 | return gv100_qctl_whitelist; |
5697 | } | 5697 | } |
5698 | 5698 | ||
5699 | int gv100_get_qctl_whitelist_count(void) | 5699 | u64 gv100_get_qctl_whitelist_count(void) |
5700 | { | 5700 | { |
5701 | return gv100_qctl_whitelist_count; | 5701 | return gv100_qctl_whitelist_count; |
5702 | } | 5702 | } |
@@ -5706,7 +5706,7 @@ const struct regop_offset_range *gv100_get_qctl_whitelist_ranges(void) | |||
5706 | return gv100_qctl_whitelist_ranges; | 5706 | return gv100_qctl_whitelist_ranges; |
5707 | } | 5707 | } |
5708 | 5708 | ||
5709 | int gv100_get_qctl_whitelist_ranges_count(void) | 5709 | u64 gv100_get_qctl_whitelist_ranges_count(void) |
5710 | { | 5710 | { |
5711 | return gv100_qctl_whitelist_ranges_count; | 5711 | return gv100_qctl_whitelist_ranges_count; |
5712 | } | 5712 | } |
diff --git a/drivers/gpu/nvgpu/gv100/regops_gv100.h b/drivers/gpu/nvgpu/gv100/regops_gv100.h index 06e5b8e1..4abfeaac 100644 --- a/drivers/gpu/nvgpu/gv100/regops_gv100.h +++ b/drivers/gpu/nvgpu/gv100/regops_gv100.h | |||
@@ -2,7 +2,7 @@ | |||
2 | * | 2 | * |
3 | * Tegra GV100 GPU Driver Register Ops | 3 | * Tegra GV100 GPU Driver Register Ops |
4 | * | 4 | * |
5 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 5 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. |
6 | * | 6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | 7 | * Permission is hereby granted, free of charge, to any person obtaining a |
8 | * copy of this software and associated documentation files (the "Software"), | 8 | * copy of this software and associated documentation files (the "Software"), |
@@ -26,17 +26,17 @@ | |||
26 | #define __REGOPS_GV100_H_ | 26 | #define __REGOPS_GV100_H_ |
27 | 27 | ||
28 | const struct regop_offset_range *gv100_get_global_whitelist_ranges(void); | 28 | const struct regop_offset_range *gv100_get_global_whitelist_ranges(void); |
29 | int gv100_get_global_whitelist_ranges_count(void); | 29 | u64 gv100_get_global_whitelist_ranges_count(void); |
30 | const struct regop_offset_range *gv100_get_context_whitelist_ranges(void); | 30 | const struct regop_offset_range *gv100_get_context_whitelist_ranges(void); |
31 | int gv100_get_context_whitelist_ranges_count(void); | 31 | u64 gv100_get_context_whitelist_ranges_count(void); |
32 | const u32 *gv100_get_runcontrol_whitelist(void); | 32 | const u32 *gv100_get_runcontrol_whitelist(void); |
33 | int gv100_get_runcontrol_whitelist_count(void); | 33 | u64 gv100_get_runcontrol_whitelist_count(void); |
34 | const struct regop_offset_range *gv100_get_runcontrol_whitelist_ranges(void); | 34 | const struct regop_offset_range *gv100_get_runcontrol_whitelist_ranges(void); |
35 | int gv100_get_runcontrol_whitelist_ranges_count(void); | 35 | u64 gv100_get_runcontrol_whitelist_ranges_count(void); |
36 | const u32 *gv100_get_qctl_whitelist(void); | 36 | const u32 *gv100_get_qctl_whitelist(void); |
37 | int gv100_get_qctl_whitelist_count(void); | 37 | u64 gv100_get_qctl_whitelist_count(void); |
38 | const struct regop_offset_range *gv100_get_qctl_whitelist_ranges(void); | 38 | const struct regop_offset_range *gv100_get_qctl_whitelist_ranges(void); |
39 | int gv100_get_qctl_whitelist_ranges_count(void); | 39 | u64 gv100_get_qctl_whitelist_ranges_count(void); |
40 | int gv100_apply_smpc_war(struct dbg_session_gk20a *dbg_s); | 40 | int gv100_apply_smpc_war(struct dbg_session_gk20a *dbg_s); |
41 | 41 | ||
42 | #endif /* __REGOPS_GV11B_H_ */ | 42 | #endif /* __REGOPS_GV11B_H_ */ |
diff --git a/drivers/gpu/nvgpu/gv11b/regops_gv11b.c b/drivers/gpu/nvgpu/gv11b/regops_gv11b.c index f84b5066..768674fe 100644 --- a/drivers/gpu/nvgpu/gv11b/regops_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/regops_gv11b.c | |||
@@ -1441,7 +1441,7 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { | |||
1441 | }; | 1441 | }; |
1442 | 1442 | ||
1443 | 1443 | ||
1444 | static const u32 gv11b_global_whitelist_ranges_count = | 1444 | static const u64 gv11b_global_whitelist_ranges_count = |
1445 | ARRAY_SIZE(gv11b_global_whitelist_ranges); | 1445 | ARRAY_SIZE(gv11b_global_whitelist_ranges); |
1446 | 1446 | ||
1447 | /* context */ | 1447 | /* context */ |
@@ -1449,24 +1449,24 @@ static const u32 gv11b_global_whitelist_ranges_count = | |||
1449 | /* runcontrol */ | 1449 | /* runcontrol */ |
1450 | static const u32 gv11b_runcontrol_whitelist[] = { | 1450 | static const u32 gv11b_runcontrol_whitelist[] = { |
1451 | }; | 1451 | }; |
1452 | static const u32 gv11b_runcontrol_whitelist_count = | 1452 | static const u64 gv11b_runcontrol_whitelist_count = |
1453 | ARRAY_SIZE(gv11b_runcontrol_whitelist); | 1453 | ARRAY_SIZE(gv11b_runcontrol_whitelist); |
1454 | 1454 | ||
1455 | static const struct regop_offset_range gv11b_runcontrol_whitelist_ranges[] = { | 1455 | static const struct regop_offset_range gv11b_runcontrol_whitelist_ranges[] = { |
1456 | }; | 1456 | }; |
1457 | static const u32 gv11b_runcontrol_whitelist_ranges_count = | 1457 | static const u64 gv11b_runcontrol_whitelist_ranges_count = |
1458 | ARRAY_SIZE(gv11b_runcontrol_whitelist_ranges); | 1458 | ARRAY_SIZE(gv11b_runcontrol_whitelist_ranges); |
1459 | 1459 | ||
1460 | 1460 | ||
1461 | /* quad ctl */ | 1461 | /* quad ctl */ |
1462 | static const u32 gv11b_qctl_whitelist[] = { | 1462 | static const u32 gv11b_qctl_whitelist[] = { |
1463 | }; | 1463 | }; |
1464 | static const u32 gv11b_qctl_whitelist_count = | 1464 | static const u64 gv11b_qctl_whitelist_count = |
1465 | ARRAY_SIZE(gv11b_qctl_whitelist); | 1465 | ARRAY_SIZE(gv11b_qctl_whitelist); |
1466 | 1466 | ||
1467 | static const struct regop_offset_range gv11b_qctl_whitelist_ranges[] = { | 1467 | static const struct regop_offset_range gv11b_qctl_whitelist_ranges[] = { |
1468 | }; | 1468 | }; |
1469 | static const u32 gv11b_qctl_whitelist_ranges_count = | 1469 | static const u64 gv11b_qctl_whitelist_ranges_count = |
1470 | ARRAY_SIZE(gv11b_qctl_whitelist_ranges); | 1470 | ARRAY_SIZE(gv11b_qctl_whitelist_ranges); |
1471 | 1471 | ||
1472 | const struct regop_offset_range *gv11b_get_global_whitelist_ranges(void) | 1472 | const struct regop_offset_range *gv11b_get_global_whitelist_ranges(void) |
@@ -1474,7 +1474,7 @@ const struct regop_offset_range *gv11b_get_global_whitelist_ranges(void) | |||
1474 | return gv11b_global_whitelist_ranges; | 1474 | return gv11b_global_whitelist_ranges; |
1475 | } | 1475 | } |
1476 | 1476 | ||
1477 | int gv11b_get_global_whitelist_ranges_count(void) | 1477 | u64 gv11b_get_global_whitelist_ranges_count(void) |
1478 | { | 1478 | { |
1479 | return gv11b_global_whitelist_ranges_count; | 1479 | return gv11b_global_whitelist_ranges_count; |
1480 | } | 1480 | } |
@@ -1484,7 +1484,7 @@ const struct regop_offset_range *gv11b_get_context_whitelist_ranges(void) | |||
1484 | return gv11b_global_whitelist_ranges; | 1484 | return gv11b_global_whitelist_ranges; |
1485 | } | 1485 | } |
1486 | 1486 | ||
1487 | int gv11b_get_context_whitelist_ranges_count(void) | 1487 | u64 gv11b_get_context_whitelist_ranges_count(void) |
1488 | { | 1488 | { |
1489 | return gv11b_global_whitelist_ranges_count; | 1489 | return gv11b_global_whitelist_ranges_count; |
1490 | } | 1490 | } |
@@ -1494,7 +1494,7 @@ const u32 *gv11b_get_runcontrol_whitelist(void) | |||
1494 | return gv11b_runcontrol_whitelist; | 1494 | return gv11b_runcontrol_whitelist; |
1495 | } | 1495 | } |
1496 | 1496 | ||
1497 | int gv11b_get_runcontrol_whitelist_count(void) | 1497 | u64 gv11b_get_runcontrol_whitelist_count(void) |
1498 | { | 1498 | { |
1499 | return gv11b_runcontrol_whitelist_count; | 1499 | return gv11b_runcontrol_whitelist_count; |
1500 | } | 1500 | } |
@@ -1504,7 +1504,7 @@ const struct regop_offset_range *gv11b_get_runcontrol_whitelist_ranges(void) | |||
1504 | return gv11b_runcontrol_whitelist_ranges; | 1504 | return gv11b_runcontrol_whitelist_ranges; |
1505 | } | 1505 | } |
1506 | 1506 | ||
1507 | int gv11b_get_runcontrol_whitelist_ranges_count(void) | 1507 | u64 gv11b_get_runcontrol_whitelist_ranges_count(void) |
1508 | { | 1508 | { |
1509 | return gv11b_runcontrol_whitelist_ranges_count; | 1509 | return gv11b_runcontrol_whitelist_ranges_count; |
1510 | } | 1510 | } |
@@ -1514,7 +1514,7 @@ const u32 *gv11b_get_qctl_whitelist(void) | |||
1514 | return gv11b_qctl_whitelist; | 1514 | return gv11b_qctl_whitelist; |
1515 | } | 1515 | } |
1516 | 1516 | ||
1517 | int gv11b_get_qctl_whitelist_count(void) | 1517 | u64 gv11b_get_qctl_whitelist_count(void) |
1518 | { | 1518 | { |
1519 | return gv11b_qctl_whitelist_count; | 1519 | return gv11b_qctl_whitelist_count; |
1520 | } | 1520 | } |
@@ -1524,7 +1524,7 @@ const struct regop_offset_range *gv11b_get_qctl_whitelist_ranges(void) | |||
1524 | return gv11b_qctl_whitelist_ranges; | 1524 | return gv11b_qctl_whitelist_ranges; |
1525 | } | 1525 | } |
1526 | 1526 | ||
1527 | int gv11b_get_qctl_whitelist_ranges_count(void) | 1527 | u64 gv11b_get_qctl_whitelist_ranges_count(void) |
1528 | { | 1528 | { |
1529 | return gv11b_qctl_whitelist_ranges_count; | 1529 | return gv11b_qctl_whitelist_ranges_count; |
1530 | } | 1530 | } |
diff --git a/drivers/gpu/nvgpu/gv11b/regops_gv11b.h b/drivers/gpu/nvgpu/gv11b/regops_gv11b.h index 0ee2edfe..b605c0a6 100644 --- a/drivers/gpu/nvgpu/gv11b/regops_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/regops_gv11b.h | |||
@@ -2,7 +2,7 @@ | |||
2 | * | 2 | * |
3 | * Tegra GV11B GPU Driver Register Ops | 3 | * Tegra GV11B GPU Driver Register Ops |
4 | * | 4 | * |
5 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 5 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. |
6 | * | 6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | 7 | * Permission is hereby granted, free of charge, to any person obtaining a |
8 | * copy of this software and associated documentation files (the "Software"), | 8 | * copy of this software and associated documentation files (the "Software"), |
@@ -26,17 +26,17 @@ | |||
26 | #define __REGOPS_GV11B_H_ | 26 | #define __REGOPS_GV11B_H_ |
27 | 27 | ||
28 | const struct regop_offset_range *gv11b_get_global_whitelist_ranges(void); | 28 | const struct regop_offset_range *gv11b_get_global_whitelist_ranges(void); |
29 | int gv11b_get_global_whitelist_ranges_count(void); | 29 | u64 gv11b_get_global_whitelist_ranges_count(void); |
30 | const struct regop_offset_range *gv11b_get_context_whitelist_ranges(void); | 30 | const struct regop_offset_range *gv11b_get_context_whitelist_ranges(void); |
31 | int gv11b_get_context_whitelist_ranges_count(void); | 31 | u64 gv11b_get_context_whitelist_ranges_count(void); |
32 | const u32 *gv11b_get_runcontrol_whitelist(void); | 32 | const u32 *gv11b_get_runcontrol_whitelist(void); |
33 | int gv11b_get_runcontrol_whitelist_count(void); | 33 | u64 gv11b_get_runcontrol_whitelist_count(void); |
34 | const struct regop_offset_range *gv11b_get_runcontrol_whitelist_ranges(void); | 34 | const struct regop_offset_range *gv11b_get_runcontrol_whitelist_ranges(void); |
35 | int gv11b_get_runcontrol_whitelist_ranges_count(void); | 35 | u64 gv11b_get_runcontrol_whitelist_ranges_count(void); |
36 | const u32 *gv11b_get_qctl_whitelist(void); | 36 | const u32 *gv11b_get_qctl_whitelist(void); |
37 | int gv11b_get_qctl_whitelist_count(void); | 37 | u64 gv11b_get_qctl_whitelist_count(void); |
38 | const struct regop_offset_range *gv11b_get_qctl_whitelist_ranges(void); | 38 | const struct regop_offset_range *gv11b_get_qctl_whitelist_ranges(void); |
39 | int gv11b_get_qctl_whitelist_ranges_count(void); | 39 | u64 gv11b_get_qctl_whitelist_ranges_count(void); |
40 | int gv11b_apply_smpc_war(struct dbg_session_gk20a *dbg_s); | 40 | int gv11b_apply_smpc_war(struct dbg_session_gk20a *dbg_s); |
41 | 41 | ||
42 | #endif /* __REGOPS_GV11B_H_ */ | 42 | #endif /* __REGOPS_GV11B_H_ */ |