diff options
-rw-r--r-- | drivers/gpu/nvgpu/common/mm/gmmu.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/mm/mm.c | 16 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/mm/nvgpu_mem.c | 17 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/mm/vm.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mm_gk20a.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/mm.h | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h | 6 |
8 files changed, 30 insertions, 29 deletions
diff --git a/drivers/gpu/nvgpu/common/mm/gmmu.c b/drivers/gpu/nvgpu/common/mm/gmmu.c index 686d0e35..dbcc8ac2 100644 --- a/drivers/gpu/nvgpu/common/mm/gmmu.c +++ b/drivers/gpu/nvgpu/common/mm/gmmu.c | |||
@@ -720,7 +720,7 @@ u64 gk20a_locked_gmmu_map(struct vm_gk20a *vm, | |||
720 | * correct based on the IO coherency flag. | 720 | * correct based on the IO coherency flag. |
721 | */ | 721 | */ |
722 | if (attrs.coherent && attrs.aperture == APERTURE_SYSMEM) { | 722 | if (attrs.coherent && attrs.aperture == APERTURE_SYSMEM) { |
723 | attrs.aperture = __APERTURE_SYSMEM_COH; | 723 | attrs.aperture = APERTURE_SYSMEM_COH; |
724 | } | 724 | } |
725 | 725 | ||
726 | /* | 726 | /* |
diff --git a/drivers/gpu/nvgpu/common/mm/mm.c b/drivers/gpu/nvgpu/common/mm/mm.c index 988b1e5c..f97d9ebd 100644 --- a/drivers/gpu/nvgpu/common/mm/mm.c +++ b/drivers/gpu/nvgpu/common/mm/mm.c | |||
@@ -36,8 +36,8 @@ | |||
36 | * Attempt to find a reserved memory area to determine PTE size for the passed | 36 | * Attempt to find a reserved memory area to determine PTE size for the passed |
37 | * mapping. If no reserved area can be found use small pages. | 37 | * mapping. If no reserved area can be found use small pages. |
38 | */ | 38 | */ |
39 | u32 __get_pte_size_fixed_map(struct vm_gk20a *vm, | 39 | static u32 nvgpu_vm_get_pte_size_fixed_map(struct vm_gk20a *vm, |
40 | u64 base, u64 size) | 40 | u64 base, u64 size) |
41 | { | 41 | { |
42 | struct nvgpu_vm_area *vm_area; | 42 | struct nvgpu_vm_area *vm_area; |
43 | 43 | ||
@@ -52,8 +52,8 @@ u32 __get_pte_size_fixed_map(struct vm_gk20a *vm, | |||
52 | /* | 52 | /* |
53 | * This is for when the address space does not support unified address spaces. | 53 | * This is for when the address space does not support unified address spaces. |
54 | */ | 54 | */ |
55 | static u32 __get_pte_size_split_addr(struct vm_gk20a *vm, | 55 | static u32 nvgpu_vm_get_pte_size_split_addr(struct vm_gk20a *vm, |
56 | u64 base, u64 size) | 56 | u64 base, u64 size) |
57 | { | 57 | { |
58 | if (!base) { | 58 | if (!base) { |
59 | if (size >= vm->gmmu_page_sizes[GMMU_PAGE_SIZE_BIG]) { | 59 | if (size >= vm->gmmu_page_sizes[GMMU_PAGE_SIZE_BIG]) { |
@@ -61,7 +61,7 @@ static u32 __get_pte_size_split_addr(struct vm_gk20a *vm, | |||
61 | } | 61 | } |
62 | return GMMU_PAGE_SIZE_SMALL; | 62 | return GMMU_PAGE_SIZE_SMALL; |
63 | } else { | 63 | } else { |
64 | if (base < __nv_gmmu_va_small_page_limit()) { | 64 | if (base < nvgpu_gmmu_va_small_page_limit()) { |
65 | return GMMU_PAGE_SIZE_SMALL; | 65 | return GMMU_PAGE_SIZE_SMALL; |
66 | } else { | 66 | } else { |
67 | return GMMU_PAGE_SIZE_BIG; | 67 | return GMMU_PAGE_SIZE_BIG; |
@@ -90,7 +90,7 @@ static u32 __get_pte_size_split_addr(struct vm_gk20a *vm, | |||
90 | * - Regardless of buffer size use small pages since we have no | 90 | * - Regardless of buffer size use small pages since we have no |
91 | * - guarantee of contiguity. | 91 | * - guarantee of contiguity. |
92 | */ | 92 | */ |
93 | u32 __get_pte_size(struct vm_gk20a *vm, u64 base, u64 size) | 93 | u32 nvgpu_vm_get_pte_size(struct vm_gk20a *vm, u64 base, u64 size) |
94 | { | 94 | { |
95 | struct gk20a *g = gk20a_from_vm(vm); | 95 | struct gk20a *g = gk20a_from_vm(vm); |
96 | 96 | ||
@@ -99,11 +99,11 @@ u32 __get_pte_size(struct vm_gk20a *vm, u64 base, u64 size) | |||
99 | } | 99 | } |
100 | 100 | ||
101 | if (!nvgpu_is_enabled(g, NVGPU_MM_UNIFY_ADDRESS_SPACES)) { | 101 | if (!nvgpu_is_enabled(g, NVGPU_MM_UNIFY_ADDRESS_SPACES)) { |
102 | return __get_pte_size_split_addr(vm, base, size); | 102 | return nvgpu_vm_get_pte_size_split_addr(vm, base, size); |
103 | } | 103 | } |
104 | 104 | ||
105 | if (base) { | 105 | if (base) { |
106 | return __get_pte_size_fixed_map(vm, base, size); | 106 | return nvgpu_vm_get_pte_size_fixed_map(vm, base, size); |
107 | } | 107 | } |
108 | 108 | ||
109 | if (size >= vm->gmmu_page_sizes[GMMU_PAGE_SIZE_BIG] && | 109 | if (size >= vm->gmmu_page_sizes[GMMU_PAGE_SIZE_BIG] && |
diff --git a/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c b/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c index ab75b136..e251f3c4 100644 --- a/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c +++ b/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c | |||
@@ -33,8 +33,9 @@ | |||
33 | * will not add any checks. If you want to simply use the default coherency then | 33 | * will not add any checks. If you want to simply use the default coherency then |
34 | * use nvgpu_aperture_mask(). | 34 | * use nvgpu_aperture_mask(). |
35 | */ | 35 | */ |
36 | u32 __nvgpu_aperture_mask(struct gk20a *g, enum nvgpu_aperture aperture, | 36 | u32 nvgpu_aperture_mask_coh(struct gk20a *g, enum nvgpu_aperture aperture, |
37 | u32 sysmem_mask, u32 sysmem_coh_mask, u32 vidmem_mask) | 37 | u32 sysmem_mask, u32 sysmem_coh_mask, |
38 | u32 vidmem_mask) | ||
38 | { | 39 | { |
39 | /* | 40 | /* |
40 | * Some iGPUs treat sysmem (i.e SoC DRAM) as vidmem. In these cases the | 41 | * Some iGPUs treat sysmem (i.e SoC DRAM) as vidmem. In these cases the |
@@ -45,7 +46,7 @@ u32 __nvgpu_aperture_mask(struct gk20a *g, enum nvgpu_aperture aperture, | |||
45 | } | 46 | } |
46 | 47 | ||
47 | switch (aperture) { | 48 | switch (aperture) { |
48 | case __APERTURE_SYSMEM_COH: | 49 | case APERTURE_SYSMEM_COH: |
49 | return sysmem_coh_mask; | 50 | return sysmem_coh_mask; |
50 | case APERTURE_SYSMEM: | 51 | case APERTURE_SYSMEM: |
51 | return sysmem_mask; | 52 | return sysmem_mask; |
@@ -69,16 +70,18 @@ u32 nvgpu_aperture_mask(struct gk20a *g, struct nvgpu_mem *mem, | |||
69 | */ | 70 | */ |
70 | if (nvgpu_is_enabled(g, NVGPU_USE_COHERENT_SYSMEM) && | 71 | if (nvgpu_is_enabled(g, NVGPU_USE_COHERENT_SYSMEM) && |
71 | ap == APERTURE_SYSMEM) { | 72 | ap == APERTURE_SYSMEM) { |
72 | ap = __APERTURE_SYSMEM_COH; | 73 | ap = APERTURE_SYSMEM_COH; |
73 | } | 74 | } |
74 | 75 | ||
75 | return __nvgpu_aperture_mask(g, ap, | 76 | return nvgpu_aperture_mask_coh(g, ap, |
76 | sysmem_mask, sysmem_coh_mask, vidmem_mask); | 77 | sysmem_mask, |
78 | sysmem_coh_mask, | ||
79 | vidmem_mask); | ||
77 | } | 80 | } |
78 | 81 | ||
79 | bool nvgpu_aperture_is_sysmem(enum nvgpu_aperture ap) | 82 | bool nvgpu_aperture_is_sysmem(enum nvgpu_aperture ap) |
80 | { | 83 | { |
81 | return ap == __APERTURE_SYSMEM_COH || ap == APERTURE_SYSMEM; | 84 | return ap == APERTURE_SYSMEM_COH || ap == APERTURE_SYSMEM; |
82 | } | 85 | } |
83 | 86 | ||
84 | bool nvgpu_mem_is_sysmem(struct nvgpu_mem *mem) | 87 | bool nvgpu_mem_is_sysmem(struct nvgpu_mem *mem) |
diff --git a/drivers/gpu/nvgpu/common/mm/vm.c b/drivers/gpu/nvgpu/common/mm/vm.c index b2b83767..27667f34 100644 --- a/drivers/gpu/nvgpu/common/mm/vm.c +++ b/drivers/gpu/nvgpu/common/mm/vm.c | |||
@@ -359,8 +359,8 @@ int __nvgpu_vm_init(struct mm_gk20a *mm, | |||
359 | user_lp_vma_limit = user_vma_limit; | 359 | user_lp_vma_limit = user_vma_limit; |
360 | } else { | 360 | } else { |
361 | user_vma_start = low_hole; | 361 | user_vma_start = low_hole; |
362 | user_vma_limit = __nv_gmmu_va_small_page_limit(); | 362 | user_vma_limit = nvgpu_gmmu_va_small_page_limit(); |
363 | user_lp_vma_start = __nv_gmmu_va_small_page_limit(); | 363 | user_lp_vma_start = nvgpu_gmmu_va_small_page_limit(); |
364 | user_lp_vma_limit = vm->va_limit - kernel_reserved; | 364 | user_lp_vma_limit = vm->va_limit - kernel_reserved; |
365 | } | 365 | } |
366 | } else { | 366 | } else { |
@@ -892,7 +892,7 @@ struct nvgpu_mapped_buf *nvgpu_vm_map(struct vm_gk20a *vm, | |||
892 | if (g->mm.disable_bigpage) { | 892 | if (g->mm.disable_bigpage) { |
893 | binfo.pgsz_idx = GMMU_PAGE_SIZE_SMALL; | 893 | binfo.pgsz_idx = GMMU_PAGE_SIZE_SMALL; |
894 | } else { | 894 | } else { |
895 | binfo.pgsz_idx = __get_pte_size(vm, map_addr, | 895 | binfo.pgsz_idx = nvgpu_vm_get_pte_size(vm, map_addr, |
896 | min_t(u64, binfo.size, align)); | 896 | min_t(u64, binfo.size, align)); |
897 | } | 897 | } |
898 | map_size = map_size ? map_size : binfo.size; | 898 | map_size = map_size ? map_size : binfo.size; |
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c index 5b76f166..6d5bea30 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c | |||
@@ -220,7 +220,7 @@ static void __update_pte(struct vm_gk20a *vm, | |||
220 | pte_w[0] |= gmmu_pte_privilege_true_f(); | 220 | pte_w[0] |= gmmu_pte_privilege_true_f(); |
221 | } | 221 | } |
222 | 222 | ||
223 | pte_w[1] = __nvgpu_aperture_mask(g, attrs->aperture, | 223 | pte_w[1] = nvgpu_aperture_mask_coh(g, attrs->aperture, |
224 | gmmu_pte_aperture_sys_mem_ncoh_f(), | 224 | gmmu_pte_aperture_sys_mem_ncoh_f(), |
225 | gmmu_pte_aperture_sys_mem_coh_f(), | 225 | gmmu_pte_aperture_sys_mem_coh_f(), |
226 | gmmu_pte_aperture_video_memory_f()) | | 226 | gmmu_pte_aperture_video_memory_f()) | |
diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index 342dc486..c8f71a19 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c | |||
@@ -191,7 +191,7 @@ static void __update_pte(struct vm_gk20a *vm, | |||
191 | u32 pte_addr = attrs->aperture == APERTURE_SYSMEM ? | 191 | u32 pte_addr = attrs->aperture == APERTURE_SYSMEM ? |
192 | gmmu_new_pte_address_sys_f(phys_shifted) : | 192 | gmmu_new_pte_address_sys_f(phys_shifted) : |
193 | gmmu_new_pte_address_vid_f(phys_shifted); | 193 | gmmu_new_pte_address_vid_f(phys_shifted); |
194 | u32 pte_tgt = __nvgpu_aperture_mask(g, | 194 | u32 pte_tgt = nvgpu_aperture_mask_coh(g, |
195 | attrs->aperture, | 195 | attrs->aperture, |
196 | gmmu_new_pte_aperture_sys_mem_ncoh_f(), | 196 | gmmu_new_pte_aperture_sys_mem_ncoh_f(), |
197 | gmmu_new_pte_aperture_sys_mem_coh_f(), | 197 | gmmu_new_pte_aperture_sys_mem_coh_f(), |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/mm.h b/drivers/gpu/nvgpu/include/nvgpu/mm.h index bfce243c..45641092 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/mm.h +++ b/drivers/gpu/nvgpu/include/nvgpu/mm.h | |||
@@ -202,14 +202,12 @@ static inline int bar1_aperture_size_mb_gk20a(void) | |||
202 | * When not using unified address spaces, the bottom 56GB of the space are used | 202 | * When not using unified address spaces, the bottom 56GB of the space are used |
203 | * for small pages, and the remaining high memory is used for large pages. | 203 | * for small pages, and the remaining high memory is used for large pages. |
204 | */ | 204 | */ |
205 | static inline u64 __nv_gmmu_va_small_page_limit(void) | 205 | static inline u64 nvgpu_gmmu_va_small_page_limit(void) |
206 | { | 206 | { |
207 | return ((u64)SZ_1G * 56); | 207 | return ((u64)SZ_1G * 56U); |
208 | } | 208 | } |
209 | 209 | ||
210 | u32 __get_pte_size_fixed_map(struct vm_gk20a *vm, | 210 | u32 nvgpu_vm_get_pte_size(struct vm_gk20a *vm, u64 base, u64 size); |
211 | u64 base, u64 size); | ||
212 | u32 __get_pte_size(struct vm_gk20a *vm, u64 base, u64 size); | ||
213 | 211 | ||
214 | void nvgpu_init_mm_ce_context(struct gk20a *g); | 212 | void nvgpu_init_mm_ce_context(struct gk20a *g); |
215 | int nvgpu_init_mm_support(struct gk20a *g); | 213 | int nvgpu_init_mm_support(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h index 2b8a5fd1..07a088f0 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h +++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h | |||
@@ -56,7 +56,7 @@ enum nvgpu_aperture { | |||
56 | APERTURE_SYSMEM, | 56 | APERTURE_SYSMEM, |
57 | 57 | ||
58 | /* Don't use directly. Use APERTURE_SYSMEM, this is used internally. */ | 58 | /* Don't use directly. Use APERTURE_SYSMEM, this is used internally. */ |
59 | __APERTURE_SYSMEM_COH, | 59 | APERTURE_SYSMEM_COH, |
60 | 60 | ||
61 | APERTURE_VIDMEM | 61 | APERTURE_VIDMEM |
62 | }; | 62 | }; |
@@ -211,7 +211,7 @@ static inline const char *nvgpu_aperture_str(struct gk20a *g, | |||
211 | return "INVAL"; | 211 | return "INVAL"; |
212 | case APERTURE_SYSMEM: | 212 | case APERTURE_SYSMEM: |
213 | return "SYSMEM"; | 213 | return "SYSMEM"; |
214 | case __APERTURE_SYSMEM_COH: | 214 | case APERTURE_SYSMEM_COH: |
215 | return "SYSCOH"; | 215 | return "SYSCOH"; |
216 | case APERTURE_VIDMEM: | 216 | case APERTURE_VIDMEM: |
217 | return "VIDMEM"; | 217 | return "VIDMEM"; |
@@ -340,7 +340,7 @@ void nvgpu_memset(struct gk20a *g, struct nvgpu_mem *mem, u32 offset, | |||
340 | u64 nvgpu_mem_get_addr(struct gk20a *g, struct nvgpu_mem *mem); | 340 | u64 nvgpu_mem_get_addr(struct gk20a *g, struct nvgpu_mem *mem); |
341 | u64 nvgpu_mem_get_phys_addr(struct gk20a *g, struct nvgpu_mem *mem); | 341 | u64 nvgpu_mem_get_phys_addr(struct gk20a *g, struct nvgpu_mem *mem); |
342 | 342 | ||
343 | u32 __nvgpu_aperture_mask(struct gk20a *g, enum nvgpu_aperture aperture, | 343 | u32 nvgpu_aperture_mask_coh(struct gk20a *g, enum nvgpu_aperture aperture, |
344 | u32 sysmem_mask, u32 sysmem_coh_mask, u32 vidmem_mask); | 344 | u32 sysmem_mask, u32 sysmem_coh_mask, u32 vidmem_mask); |
345 | u32 nvgpu_aperture_mask(struct gk20a *g, struct nvgpu_mem *mem, | 345 | u32 nvgpu_aperture_mask(struct gk20a *g, struct nvgpu_mem *mem, |
346 | u32 sysmem_mask, u32 sysmem_coh_mask, u32 vidmem_mask); | 346 | u32 sysmem_mask, u32 sysmem_coh_mask, u32 vidmem_mask); |