diff options
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/mm_vgpu.c | 12 | ||||
-rw-r--r-- | include/linux/tegra_vgpu.h | 6 |
2 files changed, 2 insertions, 16 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/mm_vgpu.c b/drivers/gpu/nvgpu/vgpu/mm_vgpu.c index eb5f7749..c6780cf7 100644 --- a/drivers/gpu/nvgpu/vgpu/mm_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/mm_vgpu.c | |||
@@ -497,18 +497,10 @@ static void vgpu_mm_l2_flush(struct gk20a *g, bool invalidate) | |||
497 | 497 | ||
498 | static void vgpu_mm_tlb_invalidate(struct vm_gk20a *vm) | 498 | static void vgpu_mm_tlb_invalidate(struct vm_gk20a *vm) |
499 | { | 499 | { |
500 | struct gk20a *g = gk20a_from_vm(vm); | ||
501 | struct tegra_vgpu_cmd_msg msg; | ||
502 | struct tegra_vgpu_as_invalidate_params *p = &msg.params.as_invalidate; | ||
503 | int err; | ||
504 | |||
505 | gk20a_dbg_fn(""); | 500 | gk20a_dbg_fn(""); |
506 | 501 | ||
507 | msg.cmd = TEGRA_VGPU_CMD_AS_INVALIDATE; | 502 | gk20a_err(dev_from_vm(vm), "%s: call to RM server not supported", |
508 | msg.handle = vgpu_get_handle(g); | 503 | __func__); |
509 | p->handle = vm->handle; | ||
510 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
511 | WARN_ON(err || msg.ret); | ||
512 | } | 504 | } |
513 | 505 | ||
514 | static void vgpu_mm_mmu_set_debug_mode(struct gk20a *g, bool enable) | 506 | static void vgpu_mm_mmu_set_debug_mode(struct gk20a *g, bool enable) |
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h index b83b9669..4f1c7926 100644 --- a/include/linux/tegra_vgpu.h +++ b/include/linux/tegra_vgpu.h | |||
@@ -48,7 +48,6 @@ enum { | |||
48 | TEGRA_VGPU_CMD_AS_FREE_SHARE = 9, | 48 | TEGRA_VGPU_CMD_AS_FREE_SHARE = 9, |
49 | TEGRA_VGPU_CMD_AS_MAP = 10, | 49 | TEGRA_VGPU_CMD_AS_MAP = 10, |
50 | TEGRA_VGPU_CMD_AS_UNMAP = 11, | 50 | TEGRA_VGPU_CMD_AS_UNMAP = 11, |
51 | TEGRA_VGPU_CMD_AS_INVALIDATE = 12, | ||
52 | TEGRA_VGPU_CMD_CHANNEL_BIND = 13, | 51 | TEGRA_VGPU_CMD_CHANNEL_BIND = 13, |
53 | TEGRA_VGPU_CMD_CHANNEL_UNBIND = 14, | 52 | TEGRA_VGPU_CMD_CHANNEL_UNBIND = 14, |
54 | TEGRA_VGPU_CMD_CHANNEL_DISABLE = 15, | 53 | TEGRA_VGPU_CMD_CHANNEL_DISABLE = 15, |
@@ -193,10 +192,6 @@ struct tegra_vgpu_mem_desc { | |||
193 | u64 length; | 192 | u64 length; |
194 | }; | 193 | }; |
195 | 194 | ||
196 | struct tegra_vgpu_as_invalidate_params { | ||
197 | u64 handle; | ||
198 | }; | ||
199 | |||
200 | struct tegra_vgpu_channel_config_params { | 195 | struct tegra_vgpu_channel_config_params { |
201 | u64 handle; | 196 | u64 handle; |
202 | }; | 197 | }; |
@@ -471,7 +466,6 @@ struct tegra_vgpu_cmd_msg { | |||
471 | struct tegra_vgpu_as_bind_share_params as_bind_share; | 466 | struct tegra_vgpu_as_bind_share_params as_bind_share; |
472 | struct tegra_vgpu_as_map_params as_map; | 467 | struct tegra_vgpu_as_map_params as_map; |
473 | struct tegra_vgpu_as_map_ex_params as_map_ex; | 468 | struct tegra_vgpu_as_map_ex_params as_map_ex; |
474 | struct tegra_vgpu_as_invalidate_params as_invalidate; | ||
475 | struct tegra_vgpu_channel_config_params channel_config; | 469 | struct tegra_vgpu_channel_config_params channel_config; |
476 | struct tegra_vgpu_ramfc_params ramfc; | 470 | struct tegra_vgpu_ramfc_params ramfc; |
477 | struct tegra_vgpu_ch_ctx_params ch_ctx; | 471 | struct tegra_vgpu_ch_ctx_params ch_ctx; |