diff options
-rw-r--r-- | drivers/gpu/nvgpu/Makefile | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/Makefile.sources | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/falcon/falcon.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/sec2/sec2.c | 131 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.c | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/enabled.h | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/sec2.h | 97 |
8 files changed, 250 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index d704de83..e0fd70e6 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile | |||
@@ -215,6 +215,7 @@ nvgpu-y += \ | |||
215 | common/ltc/ltc_gm20b.o \ | 215 | common/ltc/ltc_gm20b.o \ |
216 | common/ltc/ltc_gp10b.o \ | 216 | common/ltc/ltc_gp10b.o \ |
217 | common/ltc/ltc_gv11b.o \ | 217 | common/ltc/ltc_gv11b.o \ |
218 | common/sec2/sec2.o \ | ||
218 | common/io_common.o \ | 219 | common/io_common.o \ |
219 | common/clock_gating/gm20b_gating_reglist.o \ | 220 | common/clock_gating/gm20b_gating_reglist.o \ |
220 | common/clock_gating/gp106_gating_reglist.o \ | 221 | common/clock_gating/gp106_gating_reglist.o \ |
diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index cc612e07..8f7cdcf9 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources | |||
@@ -100,6 +100,7 @@ srcs := os/posix/nvgpu.c \ | |||
100 | common/pmu/pmu_pg.c \ | 100 | common/pmu/pmu_pg.c \ |
101 | common/pmu/pmu_perfmon.c \ | 101 | common/pmu/pmu_perfmon.c \ |
102 | common/pmu/pmu_debug.c \ | 102 | common/pmu/pmu_debug.c \ |
103 | common/sec2/sec2.c \ | ||
103 | common/ptimer/ptimer.c \ | 104 | common/ptimer/ptimer.c \ |
104 | common/sync/channel_sync.c \ | 105 | common/sync/channel_sync.c \ |
105 | common/clock_gating/gm20b_gating_reglist.c \ | 106 | common/clock_gating/gm20b_gating_reglist.c \ |
diff --git a/drivers/gpu/nvgpu/common/falcon/falcon.c b/drivers/gpu/nvgpu/common/falcon/falcon.c index b1d6558a..451b8450 100644 --- a/drivers/gpu/nvgpu/common/falcon/falcon.c +++ b/drivers/gpu/nvgpu/common/falcon/falcon.c | |||
@@ -440,6 +440,8 @@ int nvgpu_flcn_sw_init(struct gk20a *g, u32 flcn_id) | |||
440 | case FALCON_ID_SEC2: | 440 | case FALCON_ID_SEC2: |
441 | flcn = &g->sec2_flcn; | 441 | flcn = &g->sec2_flcn; |
442 | flcn->flcn_id = flcn_id; | 442 | flcn->flcn_id = flcn_id; |
443 | g->sec2.flcn = &g->sec2_flcn; | ||
444 | g->sec2.g = g; | ||
443 | break; | 445 | break; |
444 | case FALCON_ID_FECS: | 446 | case FALCON_ID_FECS: |
445 | flcn = &g->fecs_flcn; | 447 | flcn = &g->fecs_flcn; |
diff --git a/drivers/gpu/nvgpu/common/sec2/sec2.c b/drivers/gpu/nvgpu/common/sec2/sec2.c new file mode 100644 index 00000000..842d39f9 --- /dev/null +++ b/drivers/gpu/nvgpu/common/sec2/sec2.c | |||
@@ -0,0 +1,131 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #include <nvgpu/gk20a.h> | ||
24 | #include <nvgpu/log.h> | ||
25 | #include <nvgpu/timers.h> | ||
26 | #include <nvgpu/sec2.h> | ||
27 | #include <nvgpu/sec2if/sec2_if_sec2.h> | ||
28 | #include <nvgpu/sec2if/sec2_if_cmn.h> | ||
29 | |||
30 | static void sec2_seq_init(struct nvgpu_sec2 *sec2) | ||
31 | { | ||
32 | u32 i = 0; | ||
33 | |||
34 | nvgpu_log_fn(sec2->g, " "); | ||
35 | |||
36 | memset(sec2->seq, 0, | ||
37 | sizeof(struct sec2_sequence) * SEC2_MAX_NUM_SEQUENCES); | ||
38 | |||
39 | memset(sec2->sec2_seq_tbl, 0, sizeof(sec2->sec2_seq_tbl)); | ||
40 | |||
41 | for (i = 0; i < SEC2_MAX_NUM_SEQUENCES; i++) { | ||
42 | sec2->seq[i].id = (u8)i; | ||
43 | } | ||
44 | } | ||
45 | |||
46 | static void nvgpu_remove_sec2_support(struct nvgpu_sec2 *sec2) | ||
47 | { | ||
48 | struct gk20a *g = sec2->g; | ||
49 | |||
50 | nvgpu_log_fn(g, " "); | ||
51 | |||
52 | nvgpu_kfree(g, sec2->seq); | ||
53 | nvgpu_mutex_destroy(&sec2->sec2_seq_lock); | ||
54 | nvgpu_mutex_destroy(&sec2->isr_mutex); | ||
55 | } | ||
56 | |||
57 | static int nvgpu_init_sec2_setup_sw(struct gk20a *g, struct nvgpu_sec2 *sec2) | ||
58 | { | ||
59 | int err = 0; | ||
60 | |||
61 | nvgpu_log_fn(g, " "); | ||
62 | |||
63 | sec2->seq = nvgpu_kzalloc(g, SEC2_MAX_NUM_SEQUENCES * | ||
64 | sizeof(struct sec2_sequence)); | ||
65 | if (sec2->seq == NULL) { | ||
66 | err = -ENOMEM; | ||
67 | goto exit; | ||
68 | } | ||
69 | |||
70 | err = nvgpu_mutex_init(&sec2->sec2_seq_lock); | ||
71 | if (err != 0) { | ||
72 | goto free_seq_alloc; | ||
73 | } | ||
74 | |||
75 | sec2_seq_init(sec2); | ||
76 | |||
77 | err = nvgpu_mutex_init(&sec2->isr_mutex); | ||
78 | if (err != 0) { | ||
79 | goto free_seq_mutex; | ||
80 | } | ||
81 | |||
82 | sec2->remove_support = nvgpu_remove_sec2_support; | ||
83 | |||
84 | goto exit; | ||
85 | |||
86 | free_seq_mutex: | ||
87 | nvgpu_mutex_destroy(&sec2->sec2_seq_lock); | ||
88 | free_seq_alloc: | ||
89 | nvgpu_kfree(g, sec2->seq); | ||
90 | |||
91 | exit: | ||
92 | return err; | ||
93 | } | ||
94 | |||
95 | int nvgpu_init_sec2_support(struct gk20a *g) | ||
96 | { | ||
97 | struct nvgpu_sec2 *sec2 = &g->sec2; | ||
98 | int err = 0; | ||
99 | |||
100 | nvgpu_log_fn(g, " "); | ||
101 | |||
102 | err = nvgpu_init_sec2_setup_sw(g, sec2); | ||
103 | if (err != 0) { | ||
104 | goto exit; | ||
105 | } | ||
106 | |||
107 | /* TBD - call SEC2 in secure mode to boot RTOS */ | ||
108 | |||
109 | exit: | ||
110 | return err; | ||
111 | } | ||
112 | |||
113 | int nvgpu_sec2_destroy(struct gk20a *g) | ||
114 | { | ||
115 | struct nvgpu_sec2 *sec2 = &g->sec2; | ||
116 | u32 i = 0; | ||
117 | |||
118 | nvgpu_log_fn(g, " "); | ||
119 | |||
120 | nvgpu_mutex_acquire(&sec2->isr_mutex); | ||
121 | sec2->isr_enabled = false; | ||
122 | nvgpu_mutex_release(&sec2->isr_mutex); | ||
123 | |||
124 | for (i = 0; i < SEC2_QUEUE_NUM; i++) { | ||
125 | nvgpu_flcn_queue_free(sec2->flcn, &sec2->queue[i]); | ||
126 | } | ||
127 | |||
128 | sec2->sec2_ready = false; | ||
129 | |||
130 | return 0; | ||
131 | } | ||
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index 39318f66..7855493d 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c | |||
@@ -93,6 +93,10 @@ int gk20a_prepare_poweroff(struct gk20a *g) | |||
93 | ret |= nvgpu_pmu_destroy(g); | 93 | ret |= nvgpu_pmu_destroy(g); |
94 | } | 94 | } |
95 | 95 | ||
96 | if (nvgpu_is_enabled(g, NVGPU_SUPPORT_SEC2_RTOS)) { | ||
97 | ret |= nvgpu_sec2_destroy(g); | ||
98 | } | ||
99 | |||
96 | ret |= gk20a_gr_suspend(g); | 100 | ret |= gk20a_gr_suspend(g); |
97 | ret |= nvgpu_mm_suspend(g); | 101 | ret |= nvgpu_mm_suspend(g); |
98 | ret |= gk20a_fifo_suspend(g); | 102 | ret |= gk20a_fifo_suspend(g); |
@@ -313,6 +317,14 @@ int gk20a_finalize_poweron(struct gk20a *g) | |||
313 | } | 317 | } |
314 | } | 318 | } |
315 | 319 | ||
320 | if (nvgpu_is_enabled(g, NVGPU_SUPPORT_SEC2_RTOS)) { | ||
321 | err = nvgpu_init_sec2_support(g); | ||
322 | if (err != 0) { | ||
323 | nvgpu_err(g, "failed to init sec2"); | ||
324 | goto done; | ||
325 | } | ||
326 | } | ||
327 | |||
316 | if (g->ops.pmu.is_pmu_supported(g)) { | 328 | if (g->ops.pmu.is_pmu_supported(g)) { |
317 | err = nvgpu_init_pmu_support(g); | 329 | err = nvgpu_init_pmu_support(g); |
318 | if (err) { | 330 | if (err) { |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h index ccf60546..074be0c3 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/enabled.h +++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h | |||
@@ -170,10 +170,13 @@ struct gk20a; | |||
170 | /* Multiple WPR support */ | 170 | /* Multiple WPR support */ |
171 | #define NVGPU_SUPPORT_MULTIPLE_WPR 68 | 171 | #define NVGPU_SUPPORT_MULTIPLE_WPR 68 |
172 | 172 | ||
173 | /* SEC2 RTOS support*/ | ||
174 | #define NVGPU_SUPPORT_SEC2_RTOS 69 | ||
175 | |||
173 | /* | 176 | /* |
174 | * Must be greater than the largest bit offset in the above list. | 177 | * Must be greater than the largest bit offset in the above list. |
175 | */ | 178 | */ |
176 | #define NVGPU_MAX_ENABLED_BITS 69 | 179 | #define NVGPU_MAX_ENABLED_BITS 70 |
177 | 180 | ||
178 | /** | 181 | /** |
179 | * nvgpu_is_enabled - Check if the passed flag is enabled. | 182 | * nvgpu_is_enabled - Check if the passed flag is enabled. |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 104d463b..bb46d85c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h | |||
@@ -67,6 +67,7 @@ struct nvgpu_gpfifo_args; | |||
67 | #include <nvgpu/sim.h> | 67 | #include <nvgpu/sim.h> |
68 | #include <nvgpu/ecc.h> | 68 | #include <nvgpu/ecc.h> |
69 | #include <nvgpu/tsg.h> | 69 | #include <nvgpu/tsg.h> |
70 | #include <nvgpu/sec2.h> | ||
70 | 71 | ||
71 | #include "gk20a/clk_gk20a.h" | 72 | #include "gk20a/clk_gk20a.h" |
72 | #include "gk20a/ce2_gk20a.h" | 73 | #include "gk20a/ce2_gk20a.h" |
@@ -1450,6 +1451,7 @@ struct gk20a { | |||
1450 | struct perf_pmupstate perf_pmu; | 1451 | struct perf_pmupstate perf_pmu; |
1451 | struct pmgr_pmupstate pmgr_pmu; | 1452 | struct pmgr_pmupstate pmgr_pmu; |
1452 | struct therm_pmupstate therm_pmu; | 1453 | struct therm_pmupstate therm_pmu; |
1454 | struct nvgpu_sec2 sec2; | ||
1453 | 1455 | ||
1454 | #ifdef CONFIG_DEBUG_FS | 1456 | #ifdef CONFIG_DEBUG_FS |
1455 | struct railgate_stats pstats; | 1457 | struct railgate_stats pstats; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/sec2.h b/drivers/gpu/nvgpu/include/nvgpu/sec2.h new file mode 100644 index 00000000..7c755841 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/sec2.h | |||
@@ -0,0 +1,97 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef NVGPU_SEC2_H | ||
24 | #define NVGPU_SEC2_H | ||
25 | |||
26 | #include <nvgpu/kmem.h> | ||
27 | #include <nvgpu/dma.h> | ||
28 | #include <nvgpu/nvgpu_mem.h> | ||
29 | #include <nvgpu/allocator.h> | ||
30 | #include <nvgpu/lock.h> | ||
31 | #include <nvgpu/flcnif_cmn.h> | ||
32 | #include <nvgpu/falcon.h> | ||
33 | |||
34 | #include <nvgpu/sec2if/sec2_cmd_if.h> | ||
35 | #include <nvgpu/sec2if/sec2_if_sec2.h> | ||
36 | |||
37 | #define NVGPU_SEC2_TRACE_BUFSIZE (32U*1024U) | ||
38 | |||
39 | #define SEC2_MAX_NUM_SEQUENCES (256U) | ||
40 | #define SEC2_SEQ_BIT_SHIFT (5U) | ||
41 | #define SEC2_SEQ_TBL_SIZE \ | ||
42 | (SEC2_MAX_NUM_SEQUENCES >> SEC2_SEQ_BIT_SHIFT) | ||
43 | |||
44 | #define SEC2_INVALID_SEQ_DESC (~0U) | ||
45 | |||
46 | enum { | ||
47 | SEC2_SEQ_STATE_FREE = 0U, | ||
48 | SEC2_SEQ_STATE_PENDING, | ||
49 | SEC2_SEQ_STATE_USED, | ||
50 | SEC2_SEQ_STATE_CANCELLED | ||
51 | }; | ||
52 | |||
53 | typedef void (*sec2_callback)(struct gk20a *, struct nv_flcn_msg_sec2 *, | ||
54 | void *, u32, u32); | ||
55 | |||
56 | struct sec2_sequence { | ||
57 | u8 id; | ||
58 | u32 state; | ||
59 | u32 desc; | ||
60 | struct nv_flcn_msg_sec2 *msg; | ||
61 | u8 *out_payload; | ||
62 | sec2_callback callback; | ||
63 | void *cb_params; | ||
64 | }; | ||
65 | |||
66 | struct nvgpu_sec2 { | ||
67 | struct gk20a *g; | ||
68 | struct nvgpu_falcon *flcn; | ||
69 | u32 falcon_id; | ||
70 | |||
71 | struct nvgpu_falcon_queue queue[SEC2_QUEUE_NUM]; | ||
72 | |||
73 | struct sec2_sequence *seq; | ||
74 | unsigned long sec2_seq_tbl[SEC2_SEQ_TBL_SIZE]; | ||
75 | u32 next_seq_desc; | ||
76 | struct nvgpu_mutex sec2_seq_lock; | ||
77 | |||
78 | bool isr_enabled; | ||
79 | struct nvgpu_mutex isr_mutex; | ||
80 | |||
81 | struct nvgpu_allocator dmem; | ||
82 | |||
83 | /* set to true once init received */ | ||
84 | bool sec2_ready; | ||
85 | |||
86 | struct nvgpu_mem trace_buf; | ||
87 | |||
88 | void (*remove_support)(struct nvgpu_sec2 *sec2); | ||
89 | |||
90 | u32 command_ack; | ||
91 | }; | ||
92 | |||
93 | /* sec2 init */ | ||
94 | int nvgpu_init_sec2_support(struct gk20a *g); | ||
95 | int nvgpu_sec2_destroy(struct gk20a *g); | ||
96 | |||
97 | #endif /* NVGPU_SEC2_H */ | ||