diff options
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 17 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.c | 4 |
3 files changed, 8 insertions, 14 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 06e7a4e6..8bdbb106 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -636,7 +636,6 @@ int gk20a_init_pmu(struct pmu_gk20a *pmu) | |||
636 | 636 | ||
637 | mutex_init(&pmu->elpg_mutex); | 637 | mutex_init(&pmu->elpg_mutex); |
638 | mutex_init(&pmu->isr_mutex); | 638 | mutex_init(&pmu->isr_mutex); |
639 | mutex_init(&pmu->isr_enable_lock); | ||
640 | mutex_init(&pmu->pmu_copy_lock); | 639 | mutex_init(&pmu->pmu_copy_lock); |
641 | mutex_init(&pmu->pmu_seq_lock); | 640 | mutex_init(&pmu->pmu_seq_lock); |
642 | 641 | ||
@@ -2076,10 +2075,10 @@ int gk20a_init_pmu_setup_hw1(struct gk20a *g) | |||
2076 | 2075 | ||
2077 | gk20a_dbg_fn(""); | 2076 | gk20a_dbg_fn(""); |
2078 | 2077 | ||
2079 | mutex_lock(&pmu->isr_enable_lock); | 2078 | mutex_lock(&pmu->isr_mutex); |
2080 | pmu_reset(pmu); | 2079 | pmu_reset(pmu); |
2081 | pmu->isr_enabled = true; | 2080 | pmu->isr_enabled = true; |
2082 | mutex_unlock(&pmu->isr_enable_lock); | 2081 | mutex_unlock(&pmu->isr_mutex); |
2083 | 2082 | ||
2084 | /* setup apertures - virtual */ | 2083 | /* setup apertures - virtual */ |
2085 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), | 2084 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), |
@@ -3192,14 +3191,12 @@ void gk20a_pmu_isr(struct gk20a *g) | |||
3192 | 3191 | ||
3193 | gk20a_dbg_fn(""); | 3192 | gk20a_dbg_fn(""); |
3194 | 3193 | ||
3195 | mutex_lock(&pmu->isr_enable_lock); | 3194 | mutex_lock(&pmu->isr_mutex); |
3196 | if (!pmu->isr_enabled) { | 3195 | if (!pmu->isr_enabled) { |
3197 | mutex_unlock(&pmu->isr_enable_lock); | 3196 | mutex_unlock(&pmu->isr_mutex); |
3198 | return; | 3197 | return; |
3199 | } | 3198 | } |
3200 | 3199 | ||
3201 | mutex_lock(&pmu->isr_mutex); | ||
3202 | |||
3203 | mask = gk20a_readl(g, pwr_falcon_irqmask_r()) & | 3200 | mask = gk20a_readl(g, pwr_falcon_irqmask_r()) & |
3204 | gk20a_readl(g, pwr_falcon_irqdest_r()); | 3201 | gk20a_readl(g, pwr_falcon_irqdest_r()); |
3205 | 3202 | ||
@@ -3210,7 +3207,6 @@ void gk20a_pmu_isr(struct gk20a *g) | |||
3210 | if (!intr || pmu->pmu_state == PMU_STATE_OFF) { | 3207 | if (!intr || pmu->pmu_state == PMU_STATE_OFF) { |
3211 | gk20a_writel(g, pwr_falcon_irqsclr_r(), intr); | 3208 | gk20a_writel(g, pwr_falcon_irqsclr_r(), intr); |
3212 | mutex_unlock(&pmu->isr_mutex); | 3209 | mutex_unlock(&pmu->isr_mutex); |
3213 | mutex_unlock(&pmu->isr_enable_lock); | ||
3214 | return; | 3210 | return; |
3215 | } | 3211 | } |
3216 | 3212 | ||
@@ -3243,7 +3239,6 @@ void gk20a_pmu_isr(struct gk20a *g) | |||
3243 | } | 3239 | } |
3244 | 3240 | ||
3245 | mutex_unlock(&pmu->isr_mutex); | 3241 | mutex_unlock(&pmu->isr_mutex); |
3246 | mutex_unlock(&pmu->isr_enable_lock); | ||
3247 | } | 3242 | } |
3248 | 3243 | ||
3249 | static bool pmu_validate_cmd(struct pmu_gk20a *pmu, struct pmu_cmd *cmd, | 3244 | static bool pmu_validate_cmd(struct pmu_gk20a *pmu, struct pmu_cmd *cmd, |
@@ -3661,10 +3656,10 @@ int gk20a_pmu_destroy(struct gk20a *g) | |||
3661 | g->pg_ungating_time_us += (u64)elpg_ungating_time; | 3656 | g->pg_ungating_time_us += (u64)elpg_ungating_time; |
3662 | g->pg_gating_cnt += gating_cnt; | 3657 | g->pg_gating_cnt += gating_cnt; |
3663 | 3658 | ||
3664 | mutex_lock(&pmu->isr_enable_lock); | 3659 | mutex_lock(&pmu->isr_mutex); |
3665 | pmu_enable(pmu, false); | 3660 | pmu_enable(pmu, false); |
3666 | pmu->isr_enabled = false; | 3661 | pmu->isr_enabled = false; |
3667 | mutex_unlock(&pmu->isr_enable_lock); | 3662 | mutex_unlock(&pmu->isr_mutex); |
3668 | 3663 | ||
3669 | pmu->pmu_state = PMU_STATE_OFF; | 3664 | pmu->pmu_state = PMU_STATE_OFF; |
3670 | pmu->pmu_ready = false; | 3665 | pmu->pmu_ready = false; |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index 694e0288..171d5bd4 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |||
@@ -1082,7 +1082,6 @@ struct pmu_gk20a { | |||
1082 | u32 load_shadow; | 1082 | u32 load_shadow; |
1083 | 1083 | ||
1084 | struct mutex isr_mutex; | 1084 | struct mutex isr_mutex; |
1085 | struct mutex isr_enable_lock; | ||
1086 | bool isr_enabled; | 1085 | bool isr_enabled; |
1087 | 1086 | ||
1088 | bool zbc_ready; | 1087 | bool zbc_ready; |
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c index 92a89f00..4ef25a13 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c | |||
@@ -1085,10 +1085,10 @@ int gm20b_init_pmu_setup_hw1(struct gk20a *g, struct flcn_bl_dmem_desc *desc, | |||
1085 | int err; | 1085 | int err; |
1086 | 1086 | ||
1087 | gk20a_dbg_fn(""); | 1087 | gk20a_dbg_fn(""); |
1088 | mutex_lock(&pmu->isr_enable_lock); | 1088 | mutex_lock(&pmu->isr_mutex); |
1089 | pmu_reset(pmu); | 1089 | pmu_reset(pmu); |
1090 | pmu->isr_enabled = true; | 1090 | pmu->isr_enabled = true; |
1091 | mutex_unlock(&pmu->isr_enable_lock); | 1091 | mutex_unlock(&pmu->isr_mutex); |
1092 | 1092 | ||
1093 | /* setup apertures - virtual */ | 1093 | /* setup apertures - virtual */ |
1094 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), | 1094 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), |