diff options
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_fll.c | 85 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_fll.h | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/pmu/pmu_fw.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/bios.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h | 2 |
7 files changed, 82 insertions, 29 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk_fll.c b/drivers/gpu/nvgpu/clk/clk_fll.c index 2f05448f..e85168e3 100644 --- a/drivers/gpu/nvgpu/clk/clk_fll.c +++ b/drivers/gpu/nvgpu/clk/clk_fll.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -25,6 +25,7 @@ | |||
25 | #include "gk20a/gk20a.h" | 25 | #include "gk20a/gk20a.h" |
26 | #include "clk.h" | 26 | #include "clk.h" |
27 | #include "clk_fll.h" | 27 | #include "clk_fll.h" |
28 | #include "clk_domain.h" | ||
28 | #include "boardobj/boardobjgrp.h" | 29 | #include "boardobj/boardobjgrp.h" |
29 | #include "boardobj/boardobjgrp_e32.h" | 30 | #include "boardobj/boardobjgrp_e32.h" |
30 | #include "ctrl/ctrlclk.h" | 31 | #include "ctrl/ctrlclk.h" |
@@ -277,19 +278,35 @@ static u32 devinit_get_fll_device_table(struct gk20a *g, | |||
277 | 278 | ||
278 | fll_id = fll_desc_table_entry.fll_device_id; | 279 | fll_id = fll_desc_table_entry.fll_device_id; |
279 | 280 | ||
280 | pvin_dev = CLK_GET_VIN_DEVICE(pvinobjs, | 281 | if ( (u8)fll_desc_table_entry.vin_idx_logic != CTRL_CLK_VIN_ID_UNDEFINED) { |
281 | (u8)fll_desc_table_entry.vin_idx_logic); | 282 | pvin_dev = CLK_GET_VIN_DEVICE(pvinobjs, |
282 | if (pvin_dev == NULL) | 283 | (u8)fll_desc_table_entry.vin_idx_logic); |
283 | return -EINVAL; | 284 | if (pvin_dev == NULL) |
284 | 285 | return -EINVAL; | |
285 | pvin_dev->flls_shared_mask |= BIT(fll_id); | 286 | else |
286 | 287 | pvin_dev->flls_shared_mask |= BIT(fll_id); | |
287 | pvin_dev = CLK_GET_VIN_DEVICE(pvinobjs, | 288 | } else { |
288 | (u8)fll_desc_table_entry.vin_idx_sram); | 289 | /* Return if Logic ADC device index is invalid*/ |
289 | if (pvin_dev == NULL) | 290 | nvgpu_err(g, "Invalid Logic ADC specified for Nafll ID"); |
290 | return -EINVAL; | 291 | return -EINVAL; |
292 | } | ||
291 | 293 | ||
292 | pvin_dev->flls_shared_mask |= BIT(fll_id); | 294 | fll_dev_data.lut_device.vselect_mode = |
295 | (u8)BIOS_GET_FIELD(fll_desc_table_entry.lut_params, | ||
296 | NV_FLL_DESC_LUT_PARAMS_VSELECT); | ||
297 | |||
298 | if ( (u8)fll_desc_table_entry.vin_idx_sram != CTRL_CLK_VIN_ID_UNDEFINED) { | ||
299 | pvin_dev = CLK_GET_VIN_DEVICE(pvinobjs, | ||
300 | (u8)fll_desc_table_entry.vin_idx_sram); | ||
301 | if (pvin_dev == NULL) | ||
302 | return -EINVAL; | ||
303 | else | ||
304 | pvin_dev->flls_shared_mask |= BIT(fll_id); | ||
305 | } else { | ||
306 | /* Make sure VSELECT mode is set correctly to _LOGIC*/ | ||
307 | if (fll_dev_data.lut_device.vselect_mode != CTRL_CLK_FLL_LUT_VSELECT_LOGIC) | ||
308 | return -EINVAL; | ||
309 | } | ||
293 | 310 | ||
294 | fll_dev_data.super.type = | 311 | fll_dev_data.super.type = |
295 | (u8)fll_desc_table_entry.fll_device_type; | 312 | (u8)fll_desc_table_entry.fll_device_type; |
@@ -305,24 +322,17 @@ static u32 devinit_get_fll_device_table(struct gk20a *g, | |||
305 | 322 | ||
306 | vbios_domain = (u32)(fll_desc_table_entry.clk_domain & | 323 | vbios_domain = (u32)(fll_desc_table_entry.clk_domain & |
307 | NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_MASK); | 324 | NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_MASK); |
308 | if (vbios_domain == 0) | 325 | fll_dev_data.clk_domain = |
309 | fll_dev_data.clk_domain = CTRL_CLK_DOMAIN_GPC2CLK; | 326 | g->ops.pmu_ver.clk.get_vbios_clk_domain(vbios_domain); |
310 | else if (vbios_domain == 1) | ||
311 | fll_dev_data.clk_domain = CTRL_CLK_DOMAIN_XBAR2CLK; | ||
312 | else if (vbios_domain == 3) | ||
313 | fll_dev_data.clk_domain = CTRL_CLK_DOMAIN_SYS2CLK; | ||
314 | else | ||
315 | continue; | ||
316 | 327 | ||
317 | fll_dev_data.rail_idx_for_lut = 0; | 328 | fll_dev_data.rail_idx_for_lut = 0; |
318 | |||
319 | fll_dev_data.vin_idx_logic = | 329 | fll_dev_data.vin_idx_logic = |
320 | (u8)fll_desc_table_entry.vin_idx_logic; | 330 | (u8)fll_desc_table_entry.vin_idx_logic; |
321 | fll_dev_data.vin_idx_sram = | 331 | fll_dev_data.vin_idx_sram = |
322 | (u8)fll_desc_table_entry.vin_idx_sram; | 332 | (u8)fll_desc_table_entry.vin_idx_sram; |
323 | fll_dev_data.lut_device.vselect_mode = | 333 | fll_dev_data.b_skip_pldiv_below_dvco_min = |
324 | (u8)BIOS_GET_FIELD(fll_desc_table_entry.lut_params, | 334 | (bool)BIOS_GET_FIELD(fll_desc_table_entry.fll_params, |
325 | NV_FLL_DESC_LUT_PARAMS_VSELECT); | 335 | NV_FLL_DESC_FLL_PARAMS_SKIP_PLDIV_BELOW_DVCO_MIN); |
326 | fll_dev_data.lut_device.hysteresis_threshold = | 336 | fll_dev_data.lut_device.hysteresis_threshold = |
327 | (u8)BIOS_GET_FIELD(fll_desc_table_entry.lut_params, | 337 | (u8)BIOS_GET_FIELD(fll_desc_table_entry.lut_params, |
328 | NV_FLL_DESC_LUT_PARAMS_HYSTERISIS_THRESHOLD); | 338 | NV_FLL_DESC_LUT_PARAMS_HYSTERISIS_THRESHOLD); |
@@ -336,7 +346,6 @@ static u32 devinit_get_fll_device_table(struct gk20a *g, | |||
336 | 346 | ||
337 | status = boardobjgrp_objinsert(&pfllobjs->super.super, | 347 | status = boardobjgrp_objinsert(&pfllobjs->super.super, |
338 | (struct boardobj *)pfll_dev, index); | 348 | (struct boardobj *)pfll_dev, index); |
339 | |||
340 | fll_tbl_entry_ptr += fll_desc_table_header.entry_size; | 349 | fll_tbl_entry_ptr += fll_desc_table_header.entry_size; |
341 | } | 350 | } |
342 | 351 | ||
@@ -345,6 +354,28 @@ done: | |||
345 | return status; | 354 | return status; |
346 | } | 355 | } |
347 | 356 | ||
357 | u32 nvgpu_clk_get_vbios_clk_domain_gv10x( u32 vbios_domain) | ||
358 | { | ||
359 | if (vbios_domain == 0) | ||
360 | return CTRL_CLK_DOMAIN_GPCCLK; | ||
361 | else if (vbios_domain == 1) | ||
362 | return CTRL_CLK_DOMAIN_XBARCLK; | ||
363 | else if (vbios_domain == 3) | ||
364 | return CTRL_CLK_DOMAIN_SYSCLK; | ||
365 | return 0; | ||
366 | } | ||
367 | |||
368 | u32 nvgpu_clk_get_vbios_clk_domain_gp10x( u32 vbios_domain) | ||
369 | { | ||
370 | if (vbios_domain == 0) | ||
371 | return CTRL_CLK_DOMAIN_GPC2CLK; | ||
372 | else if (vbios_domain == 1) | ||
373 | return CTRL_CLK_DOMAIN_XBAR2CLK; | ||
374 | else if (vbios_domain == 3) | ||
375 | return CTRL_CLK_DOMAIN_SYS2CLK; | ||
376 | return 0; | ||
377 | } | ||
378 | |||
348 | static u32 lutbroadcastslaveregister(struct gk20a *g, | 379 | static u32 lutbroadcastslaveregister(struct gk20a *g, |
349 | struct avfsfllobjs *pfllobjs, | 380 | struct avfsfllobjs *pfllobjs, |
350 | struct fll_device *pfll, | 381 | struct fll_device *pfll, |
@@ -387,6 +418,8 @@ static struct fll_device *construct_fll_device(struct gk20a *g, | |||
387 | board_obj_fll_ptr->min_freq_vfe_idx = | 418 | board_obj_fll_ptr->min_freq_vfe_idx = |
388 | pfll_dev->min_freq_vfe_idx; | 419 | pfll_dev->min_freq_vfe_idx; |
389 | board_obj_fll_ptr->freq_ctrl_idx = pfll_dev->freq_ctrl_idx; | 420 | board_obj_fll_ptr->freq_ctrl_idx = pfll_dev->freq_ctrl_idx; |
421 | board_obj_fll_ptr->b_skip_pldiv_below_dvco_min = | ||
422 | pfll_dev->b_skip_pldiv_below_dvco_min; | ||
390 | memcpy(&board_obj_fll_ptr->lut_device, &pfll_dev->lut_device, | 423 | memcpy(&board_obj_fll_ptr->lut_device, &pfll_dev->lut_device, |
391 | sizeof(struct nv_pmu_clk_lut_device_desc)); | 424 | sizeof(struct nv_pmu_clk_lut_device_desc)); |
392 | memcpy(&board_obj_fll_ptr->regime_desc, &pfll_dev->regime_desc, | 425 | memcpy(&board_obj_fll_ptr->regime_desc, &pfll_dev->regime_desc, |
@@ -427,7 +460,7 @@ static u32 fll_device_init_pmudata_super(struct gk20a *g, | |||
427 | perf_pmu_data->min_freq_vfe_idx = | 460 | perf_pmu_data->min_freq_vfe_idx = |
428 | pfll_dev->min_freq_vfe_idx; | 461 | pfll_dev->min_freq_vfe_idx; |
429 | perf_pmu_data->freq_ctrl_idx = pfll_dev->freq_ctrl_idx; | 462 | perf_pmu_data->freq_ctrl_idx = pfll_dev->freq_ctrl_idx; |
430 | 463 | perf_pmu_data->b_skip_pldiv_below_dvco_min = pfll_dev->b_skip_pldiv_below_dvco_min; | |
431 | memcpy(&perf_pmu_data->lut_device, &pfll_dev->lut_device, | 464 | memcpy(&perf_pmu_data->lut_device, &pfll_dev->lut_device, |
432 | sizeof(struct nv_pmu_clk_lut_device_desc)); | 465 | sizeof(struct nv_pmu_clk_lut_device_desc)); |
433 | memcpy(&perf_pmu_data->regime_desc, &pfll_dev->regime_desc, | 466 | memcpy(&perf_pmu_data->regime_desc, &pfll_dev->regime_desc, |
diff --git a/drivers/gpu/nvgpu/clk/clk_fll.h b/drivers/gpu/nvgpu/clk/clk_fll.h index 481ca707..79ecf5e1 100644 --- a/drivers/gpu/nvgpu/clk/clk_fll.h +++ b/drivers/gpu/nvgpu/clk/clk_fll.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -61,10 +61,15 @@ struct fll_device { | |||
61 | u8 min_freq_vfe_idx; | 61 | u8 min_freq_vfe_idx; |
62 | u8 freq_ctrl_idx; | 62 | u8 freq_ctrl_idx; |
63 | u8 target_regime_id_override; | 63 | u8 target_regime_id_override; |
64 | bool b_skip_pldiv_below_dvco_min; | ||
65 | bool b_dvco_1x; | ||
64 | struct boardobjgrpmask_e32 lut_prog_broadcast_slave_mask; | 66 | struct boardobjgrpmask_e32 lut_prog_broadcast_slave_mask; |
65 | fll_lut_broadcast_slave_register *lut_broadcast_slave_register; | 67 | fll_lut_broadcast_slave_register *lut_broadcast_slave_register; |
66 | }; | 68 | }; |
67 | 69 | ||
70 | u32 nvgpu_clk_get_vbios_clk_domain_gv10x( u32 vbios_domain); | ||
71 | u32 nvgpu_clk_get_vbios_clk_domain_gp10x( u32 vbios_domain); | ||
72 | |||
68 | #define CLK_FLL_LUT_VF_NUM_ENTRIES(pclk) \ | 73 | #define CLK_FLL_LUT_VF_NUM_ENTRIES(pclk) \ |
69 | (pclk->avfs_fllobjs.lut_num_entries) | 74 | (pclk->avfs_fllobjs.lut_num_entries) |
70 | 75 | ||
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c index ea5b21ab..cac5079e 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c | |||
@@ -1305,6 +1305,8 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu) | |||
1305 | nvgpu_volt_rail_get_voltage_gv10x; | 1305 | nvgpu_volt_rail_get_voltage_gv10x; |
1306 | g->ops.pmu_ver.volt.volt_send_load_cmd_to_pmu = | 1306 | g->ops.pmu_ver.volt.volt_send_load_cmd_to_pmu = |
1307 | nvgpu_volt_send_load_cmd_to_pmu_gv10x; | 1307 | nvgpu_volt_send_load_cmd_to_pmu_gv10x; |
1308 | g->ops.pmu_ver.clk.get_vbios_clk_domain = | ||
1309 | nvgpu_clk_get_vbios_clk_domain_gv10x; | ||
1308 | } else { | 1310 | } else { |
1309 | g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params = | 1311 | g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params = |
1310 | get_pmu_init_msg_pmu_queue_params_v4; | 1312 | get_pmu_init_msg_pmu_queue_params_v4; |
@@ -1470,6 +1472,8 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu) | |||
1470 | nvgpu_volt_rail_get_voltage_gp10x; | 1472 | nvgpu_volt_rail_get_voltage_gp10x; |
1471 | g->ops.pmu_ver.volt.volt_send_load_cmd_to_pmu = | 1473 | g->ops.pmu_ver.volt.volt_send_load_cmd_to_pmu = |
1472 | nvgpu_volt_send_load_cmd_to_pmu_gp10x; | 1474 | nvgpu_volt_send_load_cmd_to_pmu_gp10x; |
1475 | g->ops.pmu_ver.clk.get_vbios_clk_domain = | ||
1476 | nvgpu_clk_get_vbios_clk_domain_gp10x; | ||
1473 | break; | 1477 | break; |
1474 | case APP_VERSION_GM20B: | 1478 | case APP_VERSION_GM20B: |
1475 | g->ops.pmu_ver.pg_cmd_eng_buf_load_size = | 1479 | g->ops.pmu_ver.pg_cmd_eng_buf_load_size = |
diff --git a/drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h b/drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h index cfc6538a..59a542c8 100644 --- a/drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h +++ b/drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -79,7 +79,7 @@ | |||
79 | BIT(CTRL_CLK_FLL_ID_GPC4) | \ | 79 | BIT(CTRL_CLK_FLL_ID_GPC4) | \ |
80 | BIT(CTRL_CLK_FLL_ID_GPC5)) | 80 | BIT(CTRL_CLK_FLL_ID_GPC5)) |
81 | /*! | 81 | /*! |
82 | * Mask of all FLL IDs supported by RM | 82 | * Mask of all FLL IDs supported by Nvgpu driver |
83 | */ | 83 | */ |
84 | #define CTRL_CLK_FLL_ID_ALL_MASK (BIT(CTRL_CLK_FLL_ID_SYS) | \ | 84 | #define CTRL_CLK_FLL_ID_ALL_MASK (BIT(CTRL_CLK_FLL_ID_SYS) | \ |
85 | BIT(CTRL_CLK_FLL_ID_LTC) | \ | 85 | BIT(CTRL_CLK_FLL_ID_LTC) | \ |
@@ -96,4 +96,7 @@ | |||
96 | #define CTRL_CLK_FLL_REGIME_ID_FFR (0x00000001) | 96 | #define CTRL_CLK_FLL_REGIME_ID_FFR (0x00000001) |
97 | #define CTRL_CLK_FLL_REGIME_ID_FR (0x00000002) | 97 | #define CTRL_CLK_FLL_REGIME_ID_FR (0x00000002) |
98 | 98 | ||
99 | #define CTRL_CLK_FLL_LUT_VSELECT_LOGIC (0x00000000) | ||
100 | #define CTRL_CLK_FLL_LUT_VSELECT_MIN (0x00000001) | ||
101 | #define CTRL_CLK_FLL_LUT_VSELECT_SRAM (0x00000002) | ||
99 | #endif | 102 | #endif |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index e3b37747..2d1eb388 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -788,6 +788,9 @@ struct gpu_ops { | |||
788 | u8 volt_domain, u32 *pvoltage_uv); | 788 | u8 volt_domain, u32 *pvoltage_uv); |
789 | u32 (*volt_send_load_cmd_to_pmu)(struct gk20a *g); | 789 | u32 (*volt_send_load_cmd_to_pmu)(struct gk20a *g); |
790 | } volt; | 790 | } volt; |
791 | struct { | ||
792 | u32 (*get_vbios_clk_domain)(u32 vbios_domain); | ||
793 | }clk; | ||
791 | } pmu_ver; | 794 | } pmu_ver; |
792 | struct { | 795 | struct { |
793 | int (*get_netlist_name)(struct gk20a *g, int index, char *name); | 796 | int (*get_netlist_name)(struct gk20a *g, int index, char *name); |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/bios.h b/drivers/gpu/nvgpu/include/nvgpu/bios.h index 86e009a3..191f0dbd 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/bios.h +++ b/drivers/gpu/nvgpu/include/nvgpu/bios.h | |||
@@ -110,6 +110,9 @@ struct fll_descriptor_entry_10 { | |||
110 | #define NV_FLL_DESC_FLL_PARAMS_MDIV_MASK 0x1F | 110 | #define NV_FLL_DESC_FLL_PARAMS_MDIV_MASK 0x1F |
111 | #define NV_FLL_DESC_FLL_PARAMS_MDIV_SHIFT 0 | 111 | #define NV_FLL_DESC_FLL_PARAMS_MDIV_SHIFT 0 |
112 | 112 | ||
113 | #define NV_FLL_DESC_FLL_PARAMS_SKIP_PLDIV_BELOW_DVCO_MIN_MASK 0x20 | ||
114 | #define NV_FLL_DESC_FLL_PARAMS_SKIP_PLDIV_BELOW_DVCO_MIN_SHIFT 5 | ||
115 | |||
113 | #define NV_FLL_DESC_LUT_PARAMS_VSELECT_MASK 0x3 | 116 | #define NV_FLL_DESC_LUT_PARAMS_VSELECT_MASK 0x3 |
114 | #define NV_FLL_DESC_LUT_PARAMS_VSELECT_SHIFT 0 | 117 | #define NV_FLL_DESC_LUT_PARAMS_VSELECT_SHIFT 0 |
115 | 118 | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h index 81a1d72e..616aca5c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h | |||
@@ -230,6 +230,8 @@ struct nv_pmu_clk_clk_fll_device_boardobj_set { | |||
230 | struct nv_pmu_clk_regime_desc regime_desc; | 230 | struct nv_pmu_clk_regime_desc regime_desc; |
231 | u8 min_freq_vfe_idx; | 231 | u8 min_freq_vfe_idx; |
232 | u8 freq_ctrl_idx; | 232 | u8 freq_ctrl_idx; |
233 | bool b_skip_pldiv_below_dvco_min; | ||
234 | bool b_dvco_1x; | ||
233 | struct ctrl_boardobjgrp_mask_e32 lut_prog_broadcast_slave_mask; | 235 | struct ctrl_boardobjgrp_mask_e32 lut_prog_broadcast_slave_mask; |
234 | }; | 236 | }; |
235 | 237 | ||