diff options
-rw-r--r-- | drivers/gpu/nvgpu/gv100/gr_gv100.c | 53 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/gr_gv100.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 |
4 files changed, 56 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.c b/drivers/gpu/nvgpu/gv100/gr_gv100.c index 8a4b88b4..430c7cd0 100644 --- a/drivers/gpu/nvgpu/gv100/gr_gv100.c +++ b/drivers/gpu/nvgpu/gv100/gr_gv100.c | |||
@@ -294,3 +294,56 @@ void gr_gv100_load_tpc_mask(struct gk20a *g) | |||
294 | gk20a_writel(g, gr_fe_tpc_fs_r(0), u64_lo32(pes_tpc_mask)); | 294 | gk20a_writel(g, gr_fe_tpc_fs_r(0), u64_lo32(pes_tpc_mask)); |
295 | gk20a_writel(g, gr_fe_tpc_fs_r(1), u64_hi32(pes_tpc_mask)); | 295 | gk20a_writel(g, gr_fe_tpc_fs_r(1), u64_hi32(pes_tpc_mask)); |
296 | } | 296 | } |
297 | |||
298 | u32 gr_gv100_get_patch_slots(struct gk20a *g) | ||
299 | { | ||
300 | struct gr_gk20a *gr = &g->gr; | ||
301 | struct fifo_gk20a *f = &g->fifo; | ||
302 | u32 size = 0; | ||
303 | |||
304 | /* | ||
305 | * CMD to update PE table | ||
306 | */ | ||
307 | size++; | ||
308 | |||
309 | /* | ||
310 | * Update PE table contents | ||
311 | * for PE table, each patch buffer update writes 32 TPCs | ||
312 | */ | ||
313 | size += DIV_ROUND_UP(gr->tpc_count, 32); | ||
314 | |||
315 | /* | ||
316 | * Update the PL table contents | ||
317 | * For PL table, each patch buffer update configures 4 TPCs | ||
318 | */ | ||
319 | size += DIV_ROUND_UP(gr->tpc_count, 4); | ||
320 | |||
321 | /* | ||
322 | * We need this for all subcontexts | ||
323 | */ | ||
324 | size *= f->t19x.max_subctx_count; | ||
325 | |||
326 | /* | ||
327 | * Add space for a partition mode change as well | ||
328 | * reserve two slots since DYNAMIC -> STATIC requires | ||
329 | * DYNAMIC -> NONE -> STATIC | ||
330 | */ | ||
331 | size += 2; | ||
332 | |||
333 | /* | ||
334 | * Add current patch buffer size | ||
335 | */ | ||
336 | size += gr_gk20a_get_patch_slots(g); | ||
337 | |||
338 | /* | ||
339 | * Align to 4K size | ||
340 | */ | ||
341 | size = ALIGN(size, PATCH_CTX_SLOTS_PER_PAGE); | ||
342 | |||
343 | /* | ||
344 | * Increase the size to accommodate for additional TPC partition update | ||
345 | */ | ||
346 | size += 2 * PATCH_CTX_SLOTS_PER_PAGE; | ||
347 | |||
348 | return size; | ||
349 | } | ||
diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.h b/drivers/gpu/nvgpu/gv100/gr_gv100.h index 460b05ae..612f76f9 100644 --- a/drivers/gpu/nvgpu/gv100/gr_gv100.h +++ b/drivers/gpu/nvgpu/gv100/gr_gv100.h | |||
@@ -32,5 +32,5 @@ void gr_gv100_init_sm_id_table(struct gk20a *g); | |||
32 | void gr_gv100_program_sm_id_numbering(struct gk20a *g, | 32 | void gr_gv100_program_sm_id_numbering(struct gk20a *g, |
33 | u32 gpc, u32 tpc, u32 smid); | 33 | u32 gpc, u32 tpc, u32 smid); |
34 | int gr_gv100_load_smid_config(struct gk20a *g); | 34 | int gr_gv100_load_smid_config(struct gk20a *g); |
35 | 35 | u32 gr_gv100_get_patch_slots(struct gk20a *g); | |
36 | #endif | 36 | #endif |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index e51b4446..61e9e46d 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -261,6 +261,7 @@ static const struct gpu_ops gv100_ops = { | |||
261 | .get_num_pce = gv11b_ce_get_num_pce, | 261 | .get_num_pce = gv11b_ce_get_num_pce, |
262 | }, | 262 | }, |
263 | .gr = { | 263 | .gr = { |
264 | .get_patch_slots = gr_gv100_get_patch_slots, | ||
264 | .init_gpc_mmu = gr_gv11b_init_gpc_mmu, | 265 | .init_gpc_mmu = gr_gv11b_init_gpc_mmu, |
265 | .bundle_cb_defaults = gr_gv100_bundle_cb_defaults, | 266 | .bundle_cb_defaults = gr_gv100_bundle_cb_defaults, |
266 | .cb_size_default = gr_gv100_cb_size_default, | 267 | .cb_size_default = gr_gv100_cb_size_default, |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 400c2ad0..4de9786b 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -227,6 +227,7 @@ static const struct gpu_ops gv11b_ops = { | |||
227 | .get_num_pce = gv11b_ce_get_num_pce, | 227 | .get_num_pce = gv11b_ce_get_num_pce, |
228 | }, | 228 | }, |
229 | .gr = { | 229 | .gr = { |
230 | .get_patch_slots = gr_gv100_get_patch_slots, | ||
230 | .init_gpc_mmu = gr_gv11b_init_gpc_mmu, | 231 | .init_gpc_mmu = gr_gv11b_init_gpc_mmu, |
231 | .bundle_cb_defaults = gr_gv11b_bundle_cb_defaults, | 232 | .bundle_cb_defaults = gr_gv11b_bundle_cb_defaults, |
232 | .cb_size_default = gr_gv11b_cb_size_default, | 233 | .cb_size_default = gr_gv11b_cb_size_default, |