diff options
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/nvgpu_mem.c | 58 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/mm/gmmu.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fb_gk20a.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mm_gk20a.c | 53 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mm_gk20a.h | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/ltc_gm20b.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/mm_gm20b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/mm_gm20b.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/linux/nvgpu_mem.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/mm_vgpu.c | 9 |
17 files changed, 101 insertions, 74 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/nvgpu_mem.c b/drivers/gpu/nvgpu/common/linux/nvgpu_mem.c index 34fd6626..e4991d0d 100644 --- a/drivers/gpu/nvgpu/common/linux/nvgpu_mem.c +++ b/drivers/gpu/nvgpu/common/linux/nvgpu_mem.c | |||
@@ -15,6 +15,7 @@ | |||
15 | */ | 15 | */ |
16 | 16 | ||
17 | #include <nvgpu/dma.h> | 17 | #include <nvgpu/dma.h> |
18 | #include <nvgpu/gmmu.h> | ||
18 | #include <nvgpu/nvgpu_mem.h> | 19 | #include <nvgpu/nvgpu_mem.h> |
19 | #include <nvgpu/page_allocator.h> | 20 | #include <nvgpu/page_allocator.h> |
20 | #include <nvgpu/log.h> | 21 | #include <nvgpu/log.h> |
@@ -23,6 +24,8 @@ | |||
23 | 24 | ||
24 | #include <nvgpu/linux/dma.h> | 25 | #include <nvgpu/linux/dma.h> |
25 | 26 | ||
27 | #include "os_linux.h" | ||
28 | |||
26 | #include "gk20a/gk20a.h" | 29 | #include "gk20a/gk20a.h" |
27 | #include "gk20a/mm_gk20a.h" | 30 | #include "gk20a/mm_gk20a.h" |
28 | 31 | ||
@@ -247,6 +250,61 @@ void nvgpu_memset(struct gk20a *g, struct nvgpu_mem *mem, u32 offset, | |||
247 | } | 250 | } |
248 | 251 | ||
249 | /* | 252 | /* |
253 | * Obtain a SYSMEM address from a Linux SGL. This should eventually go away | ||
254 | * and/or become private to this file once all bad usages of Linux SGLs are | ||
255 | * cleaned up in the driver. | ||
256 | */ | ||
257 | u64 nvgpu_mem_get_addr_sgl(struct gk20a *g, struct scatterlist *sgl) | ||
258 | { | ||
259 | struct nvgpu_os_linux *l = container_of(g, struct nvgpu_os_linux, g); | ||
260 | |||
261 | if (!device_is_iommuable(l->dev)) | ||
262 | return g->ops.mm.gpu_phys_addr(g, NULL, sg_phys(sgl)); | ||
263 | |||
264 | if (sg_dma_address(sgl) == 0) | ||
265 | return g->ops.mm.gpu_phys_addr(g, NULL, sg_phys(sgl)); | ||
266 | |||
267 | if (sg_dma_address(sgl) == DMA_ERROR_CODE) | ||
268 | return 0; | ||
269 | |||
270 | return gk20a_mm_smmu_vaddr_translate(g, sg_dma_address(sgl)); | ||
271 | } | ||
272 | |||
273 | /* | ||
274 | * Obtain the address the GPU should use from the %mem assuming this is a SYSMEM | ||
275 | * allocation. | ||
276 | */ | ||
277 | static u64 nvgpu_mem_get_addr_sysmem(struct gk20a *g, struct nvgpu_mem *mem) | ||
278 | { | ||
279 | return nvgpu_mem_get_addr_sgl(g, mem->priv.sgt->sgl); | ||
280 | } | ||
281 | |||
282 | /* | ||
283 | * Return the base address of %mem. Handles whether this is a VIDMEM or SYSMEM | ||
284 | * allocation. | ||
285 | * | ||
286 | * %attrs can be NULL. If it is not NULL then it may be inspected to determine | ||
287 | * if the address needs to be modified before writing into a PTE. | ||
288 | */ | ||
289 | u64 nvgpu_mem_get_addr(struct gk20a *g, struct nvgpu_mem *mem) | ||
290 | { | ||
291 | struct nvgpu_page_alloc *alloc; | ||
292 | |||
293 | if (mem->aperture == APERTURE_SYSMEM) | ||
294 | return nvgpu_mem_get_addr_sysmem(g, mem); | ||
295 | |||
296 | /* | ||
297 | * Otherwise get the vidmem address. | ||
298 | */ | ||
299 | alloc = get_vidmem_page_alloc(mem->priv.sgt->sgl); | ||
300 | |||
301 | /* This API should not be used with > 1 chunks */ | ||
302 | WARN_ON(alloc->nr_chunks != 1); | ||
303 | |||
304 | return alloc->base; | ||
305 | } | ||
306 | |||
307 | /* | ||
250 | * Be careful how you use this! You are responsible for correctly freeing this | 308 | * Be careful how you use this! You are responsible for correctly freeing this |
251 | * memory. | 309 | * memory. |
252 | */ | 310 | */ |
diff --git a/drivers/gpu/nvgpu/common/mm/gmmu.c b/drivers/gpu/nvgpu/common/mm/gmmu.c index 1be87c85..30be1b85 100644 --- a/drivers/gpu/nvgpu/common/mm/gmmu.c +++ b/drivers/gpu/nvgpu/common/mm/gmmu.c | |||
@@ -201,7 +201,7 @@ u64 nvgpu_pde_phys_addr(struct gk20a *g, struct nvgpu_gmmu_pd *pd) | |||
201 | if (g->mm.has_physical_mode) | 201 | if (g->mm.has_physical_mode) |
202 | page_addr = sg_phys(pd->mem->priv.sgt->sgl); | 202 | page_addr = sg_phys(pd->mem->priv.sgt->sgl); |
203 | else | 203 | else |
204 | page_addr = nvgpu_mem_get_base_addr(g, pd->mem, 0); | 204 | page_addr = nvgpu_mem_get_addr(g, pd->mem); |
205 | 205 | ||
206 | return page_addr + pd->mem_offs; | 206 | return page_addr + pd->mem_offs; |
207 | } | 207 | } |
@@ -559,7 +559,7 @@ static int __nvgpu_gmmu_update_page_table_sysmem(struct vm_gk20a *vm, | |||
559 | sgl = sgt->sgl; | 559 | sgl = sgt->sgl; |
560 | 560 | ||
561 | if (!g->mm.bypass_smmu) { | 561 | if (!g->mm.bypass_smmu) { |
562 | u64 io_addr = g->ops.mm.get_iova_addr(g, sgl, 0); | 562 | u64 io_addr = nvgpu_mem_get_addr_sgl(g, sgl); |
563 | 563 | ||
564 | io_addr += space_to_skip; | 564 | io_addr += space_to_skip; |
565 | 565 | ||
@@ -670,7 +670,7 @@ static int __nvgpu_gmmu_update_page_table(struct vm_gk20a *vm, | |||
670 | 670 | ||
671 | phys_addr = alloc->base; | 671 | phys_addr = alloc->base; |
672 | } else | 672 | } else |
673 | phys_addr = g->ops.mm.get_iova_addr(g, sgt->sgl, 0); | 673 | phys_addr = nvgpu_mem_get_addr_sgl(g, sgt->sgl); |
674 | } | 674 | } |
675 | 675 | ||
676 | __gmmu_dbg(g, attrs, | 676 | __gmmu_dbg(g, attrs, |
diff --git a/drivers/gpu/nvgpu/gk20a/fb_gk20a.c b/drivers/gpu/nvgpu/gk20a/fb_gk20a.c index c5f9c1fd..79f469cd 100644 --- a/drivers/gpu/nvgpu/gk20a/fb_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fb_gk20a.c | |||
@@ -44,8 +44,7 @@ void fb_gk20a_reset(struct gk20a *g) | |||
44 | 44 | ||
45 | void gk20a_fb_init_hw(struct gk20a *g) | 45 | void gk20a_fb_init_hw(struct gk20a *g) |
46 | { | 46 | { |
47 | u32 addr = g->ops.mm.get_iova_addr(g, | 47 | u32 addr = nvgpu_mem_get_addr(g, &g->mm.sysmem_flush) >> 8; |
48 | g->mm.sysmem_flush.priv.sgt->sgl, 0) >> 8; | ||
49 | 48 | ||
50 | gk20a_writel(g, fb_niso_flush_sysmem_addr_r(), addr); | 49 | gk20a_writel(g, fb_niso_flush_sysmem_addr_r(), addr); |
51 | } | 50 | } |
@@ -67,7 +66,7 @@ void gk20a_fb_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb) | |||
67 | if (!g->power_on) | 66 | if (!g->power_on) |
68 | return; | 67 | return; |
69 | 68 | ||
70 | addr_lo = u64_lo32(nvgpu_mem_get_base_addr(g, pdb, 0) >> 12); | 69 | addr_lo = u64_lo32(nvgpu_mem_get_addr(g, pdb) >> 12); |
71 | 70 | ||
72 | nvgpu_mutex_acquire(&g->mm.tlb_lock); | 71 | nvgpu_mutex_acquire(&g->mm.tlb_lock); |
73 | 72 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 347ee7dd..c0fef59d 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -891,8 +891,8 @@ static int gk20a_init_fifo_setup_sw(struct gk20a *g) | |||
891 | 891 | ||
892 | for (chid = 0; chid < f->num_channels; chid++) { | 892 | for (chid = 0; chid < f->num_channels; chid++) { |
893 | f->channel[chid].userd_iova = | 893 | f->channel[chid].userd_iova = |
894 | g->ops.mm.get_iova_addr(g, f->userd.priv.sgt->sgl, 0) | 894 | nvgpu_mem_get_addr(g, &f->userd) + |
895 | + chid * f->userd_entry_size; | 895 | chid * f->userd_entry_size; |
896 | f->channel[chid].userd_gpu_va = | 896 | f->channel[chid].userd_gpu_va = |
897 | f->userd.gpu_va + chid * f->userd_entry_size; | 897 | f->userd.gpu_va + chid * f->userd_entry_size; |
898 | gk20a_init_channel_support(g, chid); | 898 | gk20a_init_channel_support(g, chid); |
@@ -3106,8 +3106,7 @@ static int gk20a_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id, | |||
3106 | old_buf = runlist->cur_buffer; | 3106 | old_buf = runlist->cur_buffer; |
3107 | new_buf = !runlist->cur_buffer; | 3107 | new_buf = !runlist->cur_buffer; |
3108 | 3108 | ||
3109 | runlist_iova = g->ops.mm.get_iova_addr( | 3109 | runlist_iova = nvgpu_mem_get_addr(g, &runlist->mem[new_buf]); |
3110 | g, runlist->mem[new_buf].priv.sgt->sgl, 0); | ||
3111 | 3110 | ||
3112 | gk20a_dbg_info("runlist_id : %d, switch to new buffer 0x%16llx", | 3111 | gk20a_dbg_info("runlist_id : %d, switch to new buffer 0x%16llx", |
3113 | runlist_id, (u64)runlist_iova); | 3112 | runlist_id, (u64)runlist_iova); |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 4517f6e0..7b998204 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -730,8 +730,6 @@ struct gpu_ops { | |||
730 | struct vm_gk20a *vm); | 730 | struct vm_gk20a *vm); |
731 | u64 (*gpu_phys_addr)(struct gk20a *g, | 731 | u64 (*gpu_phys_addr)(struct gk20a *g, |
732 | struct nvgpu_gmmu_attrs *attrs, u64 phys); | 732 | struct nvgpu_gmmu_attrs *attrs, u64 phys); |
733 | u64 (*get_iova_addr)(struct gk20a *g, struct scatterlist *sgl, | ||
734 | u32 flags); | ||
735 | size_t (*get_vidmem_size)(struct gk20a *g); | 733 | size_t (*get_vidmem_size)(struct gk20a *g); |
736 | void (*init_inst_block)(struct nvgpu_mem *inst_block, | 734 | void (*init_inst_block)(struct nvgpu_mem *inst_block, |
737 | struct vm_gk20a *vm, u32 big_page_size); | 735 | struct vm_gk20a *vm, u32 big_page_size); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 1fc57a56..497e7ee2 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -4443,7 +4443,7 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g) | |||
4443 | gk20a_dbg_fn(""); | 4443 | gk20a_dbg_fn(""); |
4444 | 4444 | ||
4445 | /* init mmu debug buffer */ | 4445 | /* init mmu debug buffer */ |
4446 | addr = g->ops.mm.get_iova_addr(g, gr->mmu_wr_mem.priv.sgt->sgl, 0); | 4446 | addr = nvgpu_mem_get_addr(g, &gr->mmu_wr_mem); |
4447 | addr >>= fb_mmu_debug_wr_addr_alignment_v(); | 4447 | addr >>= fb_mmu_debug_wr_addr_alignment_v(); |
4448 | 4448 | ||
4449 | gk20a_writel(g, fb_mmu_debug_wr_r(), | 4449 | gk20a_writel(g, fb_mmu_debug_wr_r(), |
@@ -4453,7 +4453,7 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g) | |||
4453 | fb_mmu_debug_wr_vol_false_f() | | 4453 | fb_mmu_debug_wr_vol_false_f() | |
4454 | fb_mmu_debug_wr_addr_f(addr)); | 4454 | fb_mmu_debug_wr_addr_f(addr)); |
4455 | 4455 | ||
4456 | addr = g->ops.mm.get_iova_addr(g, gr->mmu_rd_mem.priv.sgt->sgl, 0); | 4456 | addr = nvgpu_mem_get_addr(g, &gr->mmu_rd_mem); |
4457 | addr >>= fb_mmu_debug_rd_addr_alignment_v(); | 4457 | addr >>= fb_mmu_debug_rd_addr_alignment_v(); |
4458 | 4458 | ||
4459 | gk20a_writel(g, fb_mmu_debug_rd_r(), | 4459 | gk20a_writel(g, fb_mmu_debug_rd_r(), |
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c index f4395116..16fe7149 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c | |||
@@ -1383,7 +1383,7 @@ int nvgpu_vm_map_compbits(struct vm_gk20a *vm, | |||
1383 | return -EINVAL; | 1383 | return -EINVAL; |
1384 | } | 1384 | } |
1385 | 1385 | ||
1386 | *mapping_iova = gk20a_mm_iova_addr(g, mapped_buffer->sgt->sgl, 0); | 1386 | *mapping_iova = nvgpu_mem_get_addr_sgl(g, mapped_buffer->sgt->sgl); |
1387 | *compbits_win_gva = mapped_buffer->ctag_map_win_addr; | 1387 | *compbits_win_gva = mapped_buffer->ctag_map_win_addr; |
1388 | 1388 | ||
1389 | nvgpu_mutex_release(&vm->update_gmmu_lock); | 1389 | nvgpu_mutex_release(&vm->update_gmmu_lock); |
@@ -1454,30 +1454,6 @@ static int gk20a_gmmu_clear_vidmem_mem(struct gk20a *g, struct nvgpu_mem *mem) | |||
1454 | } | 1454 | } |
1455 | #endif | 1455 | #endif |
1456 | 1456 | ||
1457 | /* | ||
1458 | * If mem is in VIDMEM, return base address in vidmem | ||
1459 | * else return IOVA address for SYSMEM | ||
1460 | */ | ||
1461 | u64 nvgpu_mem_get_base_addr(struct gk20a *g, struct nvgpu_mem *mem, | ||
1462 | u32 flags) | ||
1463 | { | ||
1464 | struct nvgpu_page_alloc *alloc; | ||
1465 | u64 addr; | ||
1466 | |||
1467 | if (mem->aperture == APERTURE_VIDMEM) { | ||
1468 | alloc = get_vidmem_page_alloc(mem->priv.sgt->sgl); | ||
1469 | |||
1470 | /* This API should not be used with > 1 chunks */ | ||
1471 | WARN_ON(alloc->nr_chunks != 1); | ||
1472 | |||
1473 | addr = alloc->base; | ||
1474 | } else { | ||
1475 | addr = g->ops.mm.get_iova_addr(g, mem->priv.sgt->sgl, flags); | ||
1476 | } | ||
1477 | |||
1478 | return addr; | ||
1479 | } | ||
1480 | |||
1481 | #if defined(CONFIG_GK20A_VIDMEM) | 1457 | #if defined(CONFIG_GK20A_VIDMEM) |
1482 | static struct nvgpu_mem *get_pending_mem_desc(struct mm_gk20a *mm) | 1458 | static struct nvgpu_mem *get_pending_mem_desc(struct mm_gk20a *mm) |
1483 | { | 1459 | { |
@@ -1526,8 +1502,7 @@ dma_addr_t gk20a_mm_gpuva_to_iova_base(struct vm_gk20a *vm, u64 gpu_vaddr) | |||
1526 | nvgpu_mutex_acquire(&vm->update_gmmu_lock); | 1502 | nvgpu_mutex_acquire(&vm->update_gmmu_lock); |
1527 | buffer = __nvgpu_vm_find_mapped_buf(vm, gpu_vaddr); | 1503 | buffer = __nvgpu_vm_find_mapped_buf(vm, gpu_vaddr); |
1528 | if (buffer) | 1504 | if (buffer) |
1529 | addr = g->ops.mm.get_iova_addr(g, buffer->sgt->sgl, | 1505 | addr = nvgpu_mem_get_addr_sgl(g, buffer->sgt->sgl); |
1530 | buffer->flags); | ||
1531 | nvgpu_mutex_release(&vm->update_gmmu_lock); | 1506 | nvgpu_mutex_release(&vm->update_gmmu_lock); |
1532 | 1507 | ||
1533 | return addr; | 1508 | return addr; |
@@ -1545,21 +1520,6 @@ u64 gk20a_mm_smmu_vaddr_translate(struct gk20a *g, dma_addr_t iova) | |||
1545 | return iova; | 1520 | return iova; |
1546 | } | 1521 | } |
1547 | 1522 | ||
1548 | u64 gk20a_mm_iova_addr(struct gk20a *g, struct scatterlist *sgl, | ||
1549 | u32 flags) | ||
1550 | { | ||
1551 | if (!device_is_iommuable(dev_from_gk20a(g))) | ||
1552 | return sg_phys(sgl); | ||
1553 | |||
1554 | if (sg_dma_address(sgl) == 0) | ||
1555 | return sg_phys(sgl); | ||
1556 | |||
1557 | if (sg_dma_address(sgl) == DMA_ERROR_CODE) | ||
1558 | return 0; | ||
1559 | |||
1560 | return gk20a_mm_smmu_vaddr_translate(g, sg_dma_address(sgl)); | ||
1561 | } | ||
1562 | |||
1563 | /* for gk20a the "video memory" apertures here are misnomers. */ | 1523 | /* for gk20a the "video memory" apertures here are misnomers. */ |
1564 | static inline u32 big_valid_pde0_bits(struct gk20a *g, | 1524 | static inline u32 big_valid_pde0_bits(struct gk20a *g, |
1565 | struct nvgpu_gmmu_pd *pd, u64 addr) | 1525 | struct nvgpu_gmmu_pd *pd, u64 addr) |
@@ -2071,7 +2031,7 @@ u64 gk20a_mm_inst_block_addr(struct gk20a *g, struct nvgpu_mem *inst_block) | |||
2071 | if (g->mm.has_physical_mode) | 2031 | if (g->mm.has_physical_mode) |
2072 | addr = gk20a_mem_phys(inst_block); | 2032 | addr = gk20a_mem_phys(inst_block); |
2073 | else | 2033 | else |
2074 | addr = nvgpu_mem_get_base_addr(g, inst_block, 0); | 2034 | addr = nvgpu_mem_get_addr(g, inst_block); |
2075 | 2035 | ||
2076 | return addr; | 2036 | return addr; |
2077 | } | 2037 | } |
@@ -2194,7 +2154,7 @@ static int gk20a_init_ce_vm(struct mm_gk20a *mm) | |||
2194 | void gk20a_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block, | 2154 | void gk20a_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block, |
2195 | struct vm_gk20a *vm) | 2155 | struct vm_gk20a *vm) |
2196 | { | 2156 | { |
2197 | u64 pdb_addr = nvgpu_mem_get_base_addr(g, vm->pdb.mem, 0); | 2157 | u64 pdb_addr = nvgpu_mem_get_addr(g, vm->pdb.mem); |
2198 | u32 pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); | 2158 | u32 pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); |
2199 | u32 pdb_addr_hi = u64_hi32(pdb_addr); | 2159 | u32 pdb_addr_hi = u64_hi32(pdb_addr); |
2200 | 2160 | ||
@@ -2465,6 +2425,11 @@ u32 gk20a_mm_get_physical_addr_bits(struct gk20a *g) | |||
2465 | return 34; | 2425 | return 34; |
2466 | } | 2426 | } |
2467 | 2427 | ||
2428 | u64 gk20a_mm_gpu_phys_addr(struct gk20a *g, u64 phys, u32 flags) | ||
2429 | { | ||
2430 | return phys; | ||
2431 | } | ||
2432 | |||
2468 | const struct gk20a_mmu_level *gk20a_mm_get_mmu_levels(struct gk20a *g, | 2433 | const struct gk20a_mmu_level *gk20a_mm_get_mmu_levels(struct gk20a *g, |
2469 | u32 big_page_size) | 2434 | u32 big_page_size) |
2470 | { | 2435 | { |
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h index c56b28bb..93baa943 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h | |||
@@ -345,11 +345,8 @@ void gk20a_mm_dump_vm(struct vm_gk20a *vm, | |||
345 | 345 | ||
346 | int gk20a_mm_suspend(struct gk20a *g); | 346 | int gk20a_mm_suspend(struct gk20a *g); |
347 | 347 | ||
348 | u64 gk20a_mm_iova_addr(struct gk20a *g, struct scatterlist *sgl, | 348 | u64 gk20a_mm_gpu_phys_addr(struct gk20a *g, u64 phys, u32 flags); |
349 | u32 flags); | ||
350 | u64 gk20a_mm_smmu_vaddr_translate(struct gk20a *g, dma_addr_t iova); | 349 | u64 gk20a_mm_smmu_vaddr_translate(struct gk20a *g, dma_addr_t iova); |
351 | u64 nvgpu_mem_get_base_addr(struct gk20a *g, struct nvgpu_mem *mem, | ||
352 | u32 flags); | ||
353 | 350 | ||
354 | void gk20a_mm_ltc_isr(struct gk20a *g); | 351 | void gk20a_mm_ltc_isr(struct gk20a *g); |
355 | 352 | ||
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c index 0d69b5da..4fa1b313 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c | |||
@@ -1081,7 +1081,7 @@ static int gm20b_bootstrap_hs_flcn(struct gk20a *g) | |||
1081 | u32 *acr_ucode_header_t210_load; | 1081 | u32 *acr_ucode_header_t210_load; |
1082 | u32 *acr_ucode_data_t210_load; | 1082 | u32 *acr_ucode_data_t210_load; |
1083 | 1083 | ||
1084 | start = g->ops.mm.get_iova_addr(g, acr->ucode_blob.priv.sgt->sgl, 0); | 1084 | start = nvgpu_mem_get_addr(g, &acr->ucode_blob); |
1085 | size = acr->ucode_blob.size; | 1085 | size = acr->ucode_blob.size; |
1086 | 1086 | ||
1087 | gm20b_dbg_pmu(""); | 1087 | gm20b_dbg_pmu(""); |
diff --git a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c index 6fef01ea..74c56487 100644 --- a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c | |||
@@ -401,8 +401,8 @@ void gm20b_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr) | |||
401 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) | 401 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) |
402 | compbit_store_iova = gk20a_mem_phys(&gr->compbit_store.mem); | 402 | compbit_store_iova = gk20a_mem_phys(&gr->compbit_store.mem); |
403 | else | 403 | else |
404 | compbit_store_iova = g->ops.mm.get_iova_addr(g, | 404 | compbit_store_iova = nvgpu_mem_get_addr(g, |
405 | gr->compbit_store.mem.priv.sgt->sgl, 0); | 405 | &gr->compbit_store.mem); |
406 | 406 | ||
407 | compbit_base_post_divide64 = compbit_store_iova >> | 407 | compbit_base_post_divide64 = compbit_store_iova >> |
408 | ltc_ltcs_ltss_cbc_base_alignment_shift_v(); | 408 | ltc_ltcs_ltss_cbc_base_alignment_shift_v(); |
diff --git a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c index d436e985..bbcd6314 100644 --- a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c | |||
@@ -80,7 +80,6 @@ void gm20b_init_mm(struct gpu_ops *gops) | |||
80 | gops->mm.get_big_page_sizes = gm20b_mm_get_big_page_sizes; | 80 | gops->mm.get_big_page_sizes = gm20b_mm_get_big_page_sizes; |
81 | gops->mm.get_default_big_page_size = gm20b_mm_get_default_big_page_size; | 81 | gops->mm.get_default_big_page_size = gm20b_mm_get_default_big_page_size; |
82 | gops->mm.gpu_phys_addr = gm20b_gpu_phys_addr; | 82 | gops->mm.gpu_phys_addr = gm20b_gpu_phys_addr; |
83 | gops->mm.get_iova_addr = gk20a_mm_iova_addr; | ||
84 | gops->mm.get_physical_addr_bits = gk20a_mm_get_physical_addr_bits; | 83 | gops->mm.get_physical_addr_bits = gk20a_mm_get_physical_addr_bits; |
85 | gops->mm.get_mmu_levels = gk20a_mm_get_mmu_levels; | 84 | gops->mm.get_mmu_levels = gk20a_mm_get_mmu_levels; |
86 | gops->mm.init_pdb = gk20a_mm_init_pdb; | 85 | gops->mm.init_pdb = gk20a_mm_init_pdb; |
diff --git a/drivers/gpu/nvgpu/gm20b/mm_gm20b.h b/drivers/gpu/nvgpu/gm20b/mm_gm20b.h index 99d6c161..2bb29ea8 100644 --- a/drivers/gpu/nvgpu/gm20b/mm_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/mm_gm20b.h | |||
@@ -20,6 +20,9 @@ struct gk20a; | |||
20 | #define PDE_ADDR_START(x, y) ((x) & ~((0x1UL << (y)) - 1)) | 20 | #define PDE_ADDR_START(x, y) ((x) & ~((0x1UL << (y)) - 1)) |
21 | #define PDE_ADDR_END(x, y) ((x) | ((0x1UL << (y)) - 1)) | 21 | #define PDE_ADDR_END(x, y) ((x) | ((0x1UL << (y)) - 1)) |
22 | 22 | ||
23 | u64 gm20b_gpu_phys_addr(struct gk20a *g, | ||
24 | struct nvgpu_gmmu_attrs *attrs, u64 phys); | ||
25 | |||
23 | void gm20b_init_mm(struct gpu_ops *gops); | 26 | void gm20b_init_mm(struct gpu_ops *gops); |
24 | int gm20b_mm_mmu_vpr_info_fetch(struct gk20a *g); | 27 | int gm20b_mm_mmu_vpr_info_fetch(struct gk20a *g); |
25 | #endif | 28 | #endif |
diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index 1ac778e0..729ccc39 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c | |||
@@ -48,8 +48,7 @@ static int gp10b_init_mm_setup_hw(struct gk20a *g) | |||
48 | g->ops.fb.set_mmu_page_size(g); | 48 | g->ops.fb.set_mmu_page_size(g); |
49 | 49 | ||
50 | gk20a_writel(g, fb_niso_flush_sysmem_addr_r(), | 50 | gk20a_writel(g, fb_niso_flush_sysmem_addr_r(), |
51 | (g->ops.mm.get_iova_addr(g, g->mm.sysmem_flush.priv.sgt->sgl, 0) | 51 | nvgpu_mem_get_addr(g, &g->mm.sysmem_flush) >> 8ULL); |
52 | >> 8ULL)); | ||
53 | 52 | ||
54 | g->ops.bus.bar1_bind(g, inst_block); | 53 | g->ops.bus.bar1_bind(g, inst_block); |
55 | 54 | ||
@@ -343,7 +342,7 @@ static const struct gk20a_mmu_level *gp10b_mm_get_mmu_levels(struct gk20a *g, | |||
343 | static void gp10b_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block, | 342 | static void gp10b_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block, |
344 | struct vm_gk20a *vm) | 343 | struct vm_gk20a *vm) |
345 | { | 344 | { |
346 | u64 pdb_addr = nvgpu_mem_get_base_addr(g, vm->pdb.mem, 0); | 345 | u64 pdb_addr = nvgpu_mem_get_addr(g, vm->pdb.mem); |
347 | u32 pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); | 346 | u32 pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); |
348 | u32 pdb_addr_hi = u64_hi32(pdb_addr); | 347 | u32 pdb_addr_hi = u64_hi32(pdb_addr); |
349 | 348 | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/linux/nvgpu_mem.h b/drivers/gpu/nvgpu/include/nvgpu/linux/nvgpu_mem.h index 9c52811e..e2d4d336 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/linux/nvgpu_mem.h +++ b/drivers/gpu/nvgpu/include/nvgpu/linux/nvgpu_mem.h | |||
@@ -19,9 +19,11 @@ | |||
19 | 19 | ||
20 | struct page; | 20 | struct page; |
21 | struct sg_table; | 21 | struct sg_table; |
22 | struct scatterlist; | ||
22 | 23 | ||
23 | struct gk20a; | 24 | struct gk20a; |
24 | struct nvgpu_mem; | 25 | struct nvgpu_mem; |
26 | struct nvgpu_gmmu_attrs; | ||
25 | 27 | ||
26 | struct nvgpu_mem_priv { | 28 | struct nvgpu_mem_priv { |
27 | struct page **pages; | 29 | struct page **pages; |
@@ -29,6 +31,8 @@ struct nvgpu_mem_priv { | |||
29 | unsigned long flags; | 31 | unsigned long flags; |
30 | }; | 32 | }; |
31 | 33 | ||
34 | u64 nvgpu_mem_get_addr_sgl(struct gk20a *g, struct scatterlist *sgl); | ||
35 | |||
32 | /** | 36 | /** |
33 | * __nvgpu_mem_create_from_pages - Create an nvgpu_mem from physical pages. | 37 | * __nvgpu_mem_create_from_pages - Create an nvgpu_mem from physical pages. |
34 | * | 38 | * |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h index 4259d40f..63439e6f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h +++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h | |||
@@ -27,6 +27,7 @@ struct sg_table; | |||
27 | 27 | ||
28 | struct gk20a; | 28 | struct gk20a; |
29 | struct nvgpu_allocator; | 29 | struct nvgpu_allocator; |
30 | struct nvgpu_gmmu_attrs; | ||
30 | 31 | ||
31 | /* | 32 | /* |
32 | * Real location of a buffer - nvgpu_aperture_mask() will deduce what will be | 33 | * Real location of a buffer - nvgpu_aperture_mask() will deduce what will be |
@@ -180,6 +181,8 @@ void nvgpu_mem_wr_n(struct gk20a *g, struct nvgpu_mem *mem, u32 offset, | |||
180 | void nvgpu_memset(struct gk20a *g, struct nvgpu_mem *mem, u32 offset, | 181 | void nvgpu_memset(struct gk20a *g, struct nvgpu_mem *mem, u32 offset, |
181 | u32 c, u32 size); | 182 | u32 c, u32 size); |
182 | 183 | ||
184 | u64 nvgpu_mem_get_addr(struct gk20a *g, struct nvgpu_mem *mem); | ||
185 | |||
183 | u32 __nvgpu_aperture_mask(struct gk20a *g, enum nvgpu_aperture aperture, | 186 | u32 __nvgpu_aperture_mask(struct gk20a *g, enum nvgpu_aperture aperture, |
184 | u32 sysmem_mask, u32 vidmem_mask); | 187 | u32 sysmem_mask, u32 vidmem_mask); |
185 | u32 nvgpu_aperture_mask(struct gk20a *g, struct nvgpu_mem *mem, | 188 | u32 nvgpu_aperture_mask(struct gk20a *g, struct nvgpu_mem *mem, |
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c index 520771a7..f1ae2f1f 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | |||
@@ -308,8 +308,8 @@ static int vgpu_init_fifo_setup_sw(struct gk20a *g) | |||
308 | 308 | ||
309 | for (chid = 0; chid < f->num_channels; chid++) { | 309 | for (chid = 0; chid < f->num_channels; chid++) { |
310 | f->channel[chid].userd_iova = | 310 | f->channel[chid].userd_iova = |
311 | g->ops.mm.get_iova_addr(g, f->userd.priv.sgt->sgl, 0) | 311 | nvgpu_mem_get_addr(g, &f->userd) + |
312 | + chid * f->userd_entry_size; | 312 | chid * f->userd_entry_size; |
313 | f->channel[chid].userd_gpu_va = | 313 | f->channel[chid].userd_gpu_va = |
314 | f->userd.gpu_va + chid * f->userd_entry_size; | 314 | f->userd.gpu_va + chid * f->userd_entry_size; |
315 | 315 | ||
diff --git a/drivers/gpu/nvgpu/vgpu/mm_vgpu.c b/drivers/gpu/nvgpu/vgpu/mm_vgpu.c index a4ffc7e8..ef9e00c8 100644 --- a/drivers/gpu/nvgpu/vgpu/mm_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/mm_vgpu.c | |||
@@ -23,8 +23,11 @@ | |||
23 | 23 | ||
24 | #include <nvgpu/vgpu/vm.h> | 24 | #include <nvgpu/vgpu/vm.h> |
25 | 25 | ||
26 | #include <nvgpu/linux/nvgpu_mem.h> | ||
27 | |||
26 | #include "vgpu/vgpu.h" | 28 | #include "vgpu/vgpu.h" |
27 | #include "gk20a/mm_gk20a.h" | 29 | #include "gk20a/mm_gk20a.h" |
30 | #include "gm20b/mm_gm20b.h" | ||
28 | 31 | ||
29 | #include "common/linux/vm_priv.h" | 32 | #include "common/linux/vm_priv.h" |
30 | 33 | ||
@@ -95,7 +98,7 @@ static u64 vgpu_locked_gmmu_map(struct vm_gk20a *vm, | |||
95 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(d); | 98 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(d); |
96 | struct tegra_vgpu_cmd_msg msg; | 99 | struct tegra_vgpu_cmd_msg msg; |
97 | struct tegra_vgpu_as_map_params *p = &msg.params.as_map; | 100 | struct tegra_vgpu_as_map_params *p = &msg.params.as_map; |
98 | u64 addr = g->ops.mm.get_iova_addr(g, sgt->sgl, flags); | 101 | u64 addr = nvgpu_mem_get_addr_sgl(g, sgt->sgl); |
99 | u8 prot; | 102 | u8 prot; |
100 | 103 | ||
101 | gk20a_dbg_fn(""); | 104 | gk20a_dbg_fn(""); |
@@ -243,7 +246,7 @@ u64 vgpu_bar1_map(struct gk20a *g, struct sg_table **sgt, u64 size) | |||
243 | { | 246 | { |
244 | struct dma_iommu_mapping *mapping = | 247 | struct dma_iommu_mapping *mapping = |
245 | to_dma_iommu_mapping(dev_from_gk20a(g)); | 248 | to_dma_iommu_mapping(dev_from_gk20a(g)); |
246 | u64 addr = g->ops.mm.get_iova_addr(g, (*sgt)->sgl, 0); | 249 | u64 addr = nvgpu_mem_get_addr_sgl(g, (*sgt)->sgl); |
247 | struct tegra_vgpu_cmd_msg msg; | 250 | struct tegra_vgpu_cmd_msg msg; |
248 | struct tegra_vgpu_as_map_params *p = &msg.params.as_map; | 251 | struct tegra_vgpu_as_map_params *p = &msg.params.as_map; |
249 | int err; | 252 | int err; |
@@ -368,6 +371,6 @@ void vgpu_init_mm_ops(struct gpu_ops *gops) | |||
368 | gops->mm.l2_flush = vgpu_mm_l2_flush; | 371 | gops->mm.l2_flush = vgpu_mm_l2_flush; |
369 | gops->fb.tlb_invalidate = vgpu_mm_tlb_invalidate; | 372 | gops->fb.tlb_invalidate = vgpu_mm_tlb_invalidate; |
370 | gops->mm.get_physical_addr_bits = gk20a_mm_get_physical_addr_bits; | 373 | gops->mm.get_physical_addr_bits = gk20a_mm_get_physical_addr_bits; |
371 | gops->mm.get_iova_addr = gk20a_mm_iova_addr; | 374 | gops->mm.gpu_phys_addr = gm20b_gpu_phys_addr; |
372 | gops->mm.init_mm_setup_hw = NULL; | 375 | gops->mm.init_mm_setup_hw = NULL; |
373 | } | 376 | } |