diff options
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/clk_gk20a.c | 26 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 26 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/clk_gp106.c | 16 |
3 files changed, 54 insertions, 14 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/clk_gk20a.c b/drivers/gpu/nvgpu/gk20a/clk_gk20a.c index 24bb8eda..38d4b555 100644 --- a/drivers/gpu/nvgpu/gk20a/clk_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/clk_gk20a.c | |||
@@ -419,22 +419,30 @@ static int gk20a_init_clk_setup_sw(struct gk20a *g) | |||
419 | static int initialized; | 419 | static int initialized; |
420 | struct clk *ref; | 420 | struct clk *ref; |
421 | unsigned long ref_rate; | 421 | unsigned long ref_rate; |
422 | int err; | ||
422 | 423 | ||
423 | gk20a_dbg_fn(""); | 424 | gk20a_dbg_fn(""); |
424 | 425 | ||
426 | err = nvgpu_mutex_init(&clk->clk_mutex); | ||
427 | if (err) | ||
428 | return err; | ||
429 | |||
425 | if (clk->sw_ready) { | 430 | if (clk->sw_ready) { |
426 | gk20a_dbg_fn("skip init"); | 431 | gk20a_dbg_fn("skip init"); |
427 | return 0; | 432 | return 0; |
428 | } | 433 | } |
429 | 434 | ||
430 | if (!gk20a_clk_get(g)) | 435 | if (!gk20a_clk_get(g)) { |
431 | return -EINVAL; | 436 | err = -EINVAL; |
437 | goto fail; | ||
438 | } | ||
432 | 439 | ||
433 | ref = clk_get_parent(clk_get_parent(clk->tegra_clk)); | 440 | ref = clk_get_parent(clk_get_parent(clk->tegra_clk)); |
434 | if (IS_ERR(ref)) { | 441 | if (IS_ERR(ref)) { |
435 | gk20a_err(dev_from_gk20a(g), | 442 | gk20a_err(dev_from_gk20a(g), |
436 | "failed to get GPCPLL reference clock"); | 443 | "failed to get GPCPLL reference clock"); |
437 | return -EINVAL; | 444 | err = -EINVAL; |
445 | goto fail; | ||
438 | } | 446 | } |
439 | ref_rate = clk_get_rate(ref); | 447 | ref_rate = clk_get_rate(ref); |
440 | 448 | ||
@@ -443,7 +451,8 @@ static int gk20a_init_clk_setup_sw(struct gk20a *g) | |||
443 | if (clk->gpc_pll.clk_in == 0) { | 451 | if (clk->gpc_pll.clk_in == 0) { |
444 | gk20a_err(dev_from_gk20a(g), | 452 | gk20a_err(dev_from_gk20a(g), |
445 | "GPCPLL reference clock is zero"); | 453 | "GPCPLL reference clock is zero"); |
446 | return -EINVAL; | 454 | err = -EINVAL; |
455 | goto fail; | ||
447 | } | 456 | } |
448 | 457 | ||
449 | /* Decide initial frequency */ | 458 | /* Decide initial frequency */ |
@@ -457,12 +466,14 @@ static int gk20a_init_clk_setup_sw(struct gk20a *g) | |||
457 | clk->gpc_pll.freq /= pl_to_div[clk->gpc_pll.PL]; | 466 | clk->gpc_pll.freq /= pl_to_div[clk->gpc_pll.PL]; |
458 | } | 467 | } |
459 | 468 | ||
460 | nvgpu_mutex_init(&clk->clk_mutex); | ||
461 | |||
462 | clk->sw_ready = true; | 469 | clk->sw_ready = true; |
463 | 470 | ||
464 | gk20a_dbg_fn("done"); | 471 | gk20a_dbg_fn("done"); |
465 | return 0; | 472 | return 0; |
473 | |||
474 | fail: | ||
475 | nvgpu_mutex_destroy(&clk->clk_mutex); | ||
476 | return err; | ||
466 | } | 477 | } |
467 | 478 | ||
468 | static int gk20a_init_clk_setup_hw(struct gk20a *g) | 479 | static int gk20a_init_clk_setup_hw(struct gk20a *g) |
@@ -684,6 +695,9 @@ static int gk20a_suspend_clk_support(struct gk20a *g) | |||
684 | ret = clk_disable_gpcpll(g, 1); | 695 | ret = clk_disable_gpcpll(g, 1); |
685 | g->clk.clk_hw_on = false; | 696 | g->clk.clk_hw_on = false; |
686 | nvgpu_mutex_release(&g->clk.clk_mutex); | 697 | nvgpu_mutex_release(&g->clk.clk_mutex); |
698 | |||
699 | nvgpu_mutex_destroy(&g->clk.clk_mutex); | ||
700 | |||
687 | return ret; | 701 | return ret; |
688 | } | 702 | } |
689 | 703 | ||
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index d6eec0a5..451dd7b6 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c | |||
@@ -1122,16 +1122,23 @@ static int gm20b_init_clk_setup_sw(struct gk20a *g) | |||
1122 | struct clk_gk20a *clk = &g->clk; | 1122 | struct clk_gk20a *clk = &g->clk; |
1123 | unsigned long safe_rate; | 1123 | unsigned long safe_rate; |
1124 | struct clk *ref, *c; | 1124 | struct clk *ref, *c; |
1125 | int err; | ||
1125 | 1126 | ||
1126 | gk20a_dbg_fn(""); | 1127 | gk20a_dbg_fn(""); |
1127 | 1128 | ||
1129 | err = nvgpu_mutex_init(&clk->clk_mutex); | ||
1130 | if (err) | ||
1131 | return err; | ||
1132 | |||
1128 | if (clk->sw_ready) { | 1133 | if (clk->sw_ready) { |
1129 | gk20a_dbg_fn("skip init"); | 1134 | gk20a_dbg_fn("skip init"); |
1130 | return 0; | 1135 | return 0; |
1131 | } | 1136 | } |
1132 | 1137 | ||
1133 | if (!gk20a_clk_get(g)) | 1138 | if (!gk20a_clk_get(g)) { |
1134 | return -EINVAL; | 1139 | err = -EINVAL; |
1140 | goto fail; | ||
1141 | } | ||
1135 | 1142 | ||
1136 | /* | 1143 | /* |
1137 | * On Tegra GPU clock exposed to frequency governor is a shared user on | 1144 | * On Tegra GPU clock exposed to frequency governor is a shared user on |
@@ -1149,7 +1156,8 @@ static int gm20b_init_clk_setup_sw(struct gk20a *g) | |||
1149 | if (IS_ERR(ref)) { | 1156 | if (IS_ERR(ref)) { |
1150 | gk20a_err(dev_from_gk20a(g), | 1157 | gk20a_err(dev_from_gk20a(g), |
1151 | "failed to get GPCPLL reference clock"); | 1158 | "failed to get GPCPLL reference clock"); |
1152 | return -EINVAL; | 1159 | err = -EINVAL; |
1160 | goto fail; | ||
1153 | } | 1161 | } |
1154 | 1162 | ||
1155 | clk->gpc_pll.id = GK20A_GPC_PLL; | 1163 | clk->gpc_pll.id = GK20A_GPC_PLL; |
@@ -1157,7 +1165,8 @@ static int gm20b_init_clk_setup_sw(struct gk20a *g) | |||
1157 | if (clk->gpc_pll.clk_in == 0) { | 1165 | if (clk->gpc_pll.clk_in == 0) { |
1158 | gk20a_err(dev_from_gk20a(g), | 1166 | gk20a_err(dev_from_gk20a(g), |
1159 | "GPCPLL reference clock is zero"); | 1167 | "GPCPLL reference clock is zero"); |
1160 | return -EINVAL; | 1168 | err = -EINVAL; |
1169 | goto fail; | ||
1161 | } | 1170 | } |
1162 | 1171 | ||
1163 | safe_rate = tegra_dvfs_get_fmax_at_vmin_safe_t(c); | 1172 | safe_rate = tegra_dvfs_get_fmax_at_vmin_safe_t(c); |
@@ -1191,8 +1200,6 @@ static int gm20b_init_clk_setup_sw(struct gk20a *g) | |||
1191 | } | 1200 | } |
1192 | #endif | 1201 | #endif |
1193 | 1202 | ||
1194 | nvgpu_mutex_init(&clk->clk_mutex); | ||
1195 | |||
1196 | clk->sw_ready = true; | 1203 | clk->sw_ready = true; |
1197 | 1204 | ||
1198 | gk20a_dbg_fn("done"); | 1205 | gk20a_dbg_fn("done"); |
@@ -1200,6 +1207,10 @@ static int gm20b_init_clk_setup_sw(struct gk20a *g) | |||
1200 | clk->gpc_pll.mode == GPC_PLL_MODE_DVFS ? " NA mode," : "", | 1207 | clk->gpc_pll.mode == GPC_PLL_MODE_DVFS ? " NA mode," : "", |
1201 | clk->gpc_pll.M, clk->gpc_pll.N, clk->gpc_pll.PL); | 1208 | clk->gpc_pll.M, clk->gpc_pll.N, clk->gpc_pll.PL); |
1202 | return 0; | 1209 | return 0; |
1210 | |||
1211 | fail: | ||
1212 | nvgpu_mutex_destroy(&clk->clk_mutex); | ||
1213 | return err; | ||
1203 | } | 1214 | } |
1204 | 1215 | ||
1205 | 1216 | ||
@@ -1587,6 +1598,9 @@ static int gm20b_suspend_clk_support(struct gk20a *g) | |||
1587 | ret = clk_disable_gpcpll(g, 1); | 1598 | ret = clk_disable_gpcpll(g, 1); |
1588 | g->clk.clk_hw_on = false; | 1599 | g->clk.clk_hw_on = false; |
1589 | nvgpu_mutex_release(&g->clk.clk_mutex); | 1600 | nvgpu_mutex_release(&g->clk.clk_mutex); |
1601 | |||
1602 | nvgpu_mutex_destroy(&g->clk.clk_mutex); | ||
1603 | |||
1590 | return ret; | 1604 | return ret; |
1591 | } | 1605 | } |
1592 | 1606 | ||
diff --git a/drivers/gpu/nvgpu/gp106/clk_gp106.c b/drivers/gpu/nvgpu/gp106/clk_gp106.c index 8869c94b..8bc47ead 100644 --- a/drivers/gpu/nvgpu/gp106/clk_gp106.c +++ b/drivers/gpu/nvgpu/gp106/clk_gp106.c | |||
@@ -78,18 +78,23 @@ static int gp106_init_clk_support(struct gk20a *g) { | |||
78 | 78 | ||
79 | gk20a_dbg_fn(""); | 79 | gk20a_dbg_fn(""); |
80 | 80 | ||
81 | nvgpu_mutex_init(&clk->clk_mutex); | 81 | err = nvgpu_mutex_init(&clk->clk_mutex); |
82 | if (err) | ||
83 | return err; | ||
82 | 84 | ||
83 | clk->clk_namemap = (struct namemap_cfg *) | 85 | clk->clk_namemap = (struct namemap_cfg *) |
84 | nvgpu_kzalloc(g, sizeof(struct namemap_cfg) * NUM_NAMEMAPS); | 86 | nvgpu_kzalloc(g, sizeof(struct namemap_cfg) * NUM_NAMEMAPS); |
85 | 87 | ||
86 | if (!clk->clk_namemap) | 88 | if (!clk->clk_namemap) { |
89 | nvgpu_mutex_destroy(&clk->clk_mutex); | ||
87 | return -ENOMEM; | 90 | return -ENOMEM; |
91 | } | ||
88 | 92 | ||
89 | clk->namemap_xlat_table = nvgpu_kcalloc(g, NUM_NAMEMAPS, sizeof(u32)); | 93 | clk->namemap_xlat_table = nvgpu_kcalloc(g, NUM_NAMEMAPS, sizeof(u32)); |
90 | 94 | ||
91 | if (!clk->namemap_xlat_table) { | 95 | if (!clk->namemap_xlat_table) { |
92 | nvgpu_kfree(g, clk->clk_namemap); | 96 | nvgpu_kfree(g, clk->clk_namemap); |
97 | nvgpu_mutex_destroy(&clk->clk_mutex); | ||
93 | return -ENOMEM; | 98 | return -ENOMEM; |
94 | } | 99 | } |
95 | 100 | ||
@@ -265,8 +270,15 @@ err_out: | |||
265 | } | 270 | } |
266 | #endif /* CONFIG_DEBUG_FS */ | 271 | #endif /* CONFIG_DEBUG_FS */ |
267 | 272 | ||
273 | static int gp106_suspend_clk_support(struct gk20a *g) | ||
274 | { | ||
275 | nvgpu_mutex_destroy(&g->clk.clk_mutex); | ||
276 | return 0; | ||
277 | } | ||
278 | |||
268 | void gp106_init_clk_ops(struct gpu_ops *gops) { | 279 | void gp106_init_clk_ops(struct gpu_ops *gops) { |
269 | gops->clk.init_clk_support = gp106_init_clk_support; | 280 | gops->clk.init_clk_support = gp106_init_clk_support; |
270 | gops->clk.get_crystal_clk_hz = gp106_crystal_clk_hz; | 281 | gops->clk.get_crystal_clk_hz = gp106_crystal_clk_hz; |
271 | gops->clk.measure_freq = gp106_clk_measure_freq; | 282 | gops->clk.measure_freq = gp106_clk_measure_freq; |
283 | gops->clk.suspend_clk_support = gp106_suspend_clk_support; | ||
272 | } | 284 | } |