diff options
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifboardobj.h | 20 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperf.h | 50 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifpmgr.h | 48 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h | 44 |
4 files changed, 81 insertions, 81 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifboardobj.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifboardobj.h index a1eedc28..47226aa1 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifboardobj.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifboardobj.h | |||
@@ -26,16 +26,16 @@ | |||
26 | #include "ctrl/ctrlboardobj.h" | 26 | #include "ctrl/ctrlboardobj.h" |
27 | 27 | ||
28 | /* board object group command id's. */ | 28 | /* board object group command id's. */ |
29 | #define NV_PMU_BOARDOBJGRP_CMD_SET 0x00 | 29 | #define NV_PMU_BOARDOBJGRP_CMD_SET 0x00U |
30 | #define NV_PMU_BOARDOBJGRP_CMD_GET_STATUS 0x01 | 30 | #define NV_PMU_BOARDOBJGRP_CMD_GET_STATUS 0x01U |
31 | 31 | ||
32 | #define NV_PMU_RPC_ID_CLK_BOARD_OBJ_GRP_CMD 0x00 | 32 | #define NV_PMU_RPC_ID_CLK_BOARD_OBJ_GRP_CMD 0x00U |
33 | #define NV_PMU_RPC_ID_FAN_BOARD_OBJ_GRP_CMD 0x00 | 33 | #define NV_PMU_RPC_ID_FAN_BOARD_OBJ_GRP_CMD 0x00U |
34 | #define NV_PMU_RPC_ID_PERF_BOARD_OBJ_GRP_CMD 0x00 | 34 | #define NV_PMU_RPC_ID_PERF_BOARD_OBJ_GRP_CMD 0x00U |
35 | #define NV_PMU_RPC_ID_PERF_CF_BOARD_OBJ_GRP_CMD 0x00 | 35 | #define NV_PMU_RPC_ID_PERF_CF_BOARD_OBJ_GRP_CMD 0x00U |
36 | #define NV_PMU_RPC_ID_PMGR_BOARD_OBJ_GRP_CMD 0x00 | 36 | #define NV_PMU_RPC_ID_PMGR_BOARD_OBJ_GRP_CMD 0x00U |
37 | #define NV_PMU_RPC_ID_THERM_BOARD_OBJ_GRP_CMD 0x00 | 37 | #define NV_PMU_RPC_ID_THERM_BOARD_OBJ_GRP_CMD 0x00U |
38 | #define NV_PMU_RPC_ID_VOLT_BOARD_OBJ_GRP_CMD 0x00 | 38 | #define NV_PMU_RPC_ID_VOLT_BOARD_OBJ_GRP_CMD 0x00U |
39 | 39 | ||
40 | /* | 40 | /* |
41 | * Base structure describing a BOARDOBJ for communication between Kernel and | 41 | * Base structure describing a BOARDOBJ for communication between Kernel and |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperf.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperf.h index f7157ee9..70b93e12 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperf.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperf.h | |||
@@ -30,31 +30,31 @@ | |||
30 | * argument for communications between Kernel and PMU via the various generic | 30 | * argument for communications between Kernel and PMU via the various generic |
31 | * BOARDOBJGRP interfaces. | 31 | * BOARDOBJGRP interfaces. |
32 | */ | 32 | */ |
33 | #define NV_PMU_PERF_BOARDOBJGRP_CLASS_ID_VFE_VAR 0x00 | 33 | #define NV_PMU_PERF_BOARDOBJGRP_CLASS_ID_VFE_VAR 0x00U |
34 | #define NV_PMU_PERF_BOARDOBJGRP_CLASS_ID_VFE_EQU 0x01 | 34 | #define NV_PMU_PERF_BOARDOBJGRP_CLASS_ID_VFE_EQU 0x01U |
35 | 35 | ||
36 | #define NV_PMU_PERF_CMD_ID_RPC (0x00000002) | 36 | #define NV_PMU_PERF_CMD_ID_RPC (0x00000002U) |
37 | #define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_SET (0x00000003) | 37 | #define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_SET (0x00000003U) |
38 | #define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000004) | 38 | #define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000004U) |
39 | 39 | ||
40 | /*! | 40 | /*! |
41 | * RPC calls serviced by PERF unit. | 41 | * RPC calls serviced by PERF unit. |
42 | */ | 42 | */ |
43 | #define NV_PMU_RPC_ID_PERF_BOARD_OBJ_GRP_CMD 0x00 | 43 | #define NV_PMU_RPC_ID_PERF_BOARD_OBJ_GRP_CMD 0x00U |
44 | #define NV_PMU_RPC_ID_PERF_LOAD 0x01 | 44 | #define NV_PMU_RPC_ID_PERF_LOAD 0x01U |
45 | #define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_INFO_GET 0x02 | 45 | #define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_INFO_GET 0x02U |
46 | #define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_INFO_SET 0x03 | 46 | #define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_INFO_SET 0x03U |
47 | #define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_SET_CONTROL 0x04 | 47 | #define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_SET_CONTROL 0x04U |
48 | #define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_QUEUE_CHANGE 0x05 | 48 | #define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_QUEUE_CHANGE 0x05U |
49 | #define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_LOCK 0x06 | 49 | #define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_LOCK 0x06U |
50 | #define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_LOAD 0x07 | 50 | #define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_LOAD 0x07U |
51 | #define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_QUERY 0x08 | 51 | #define NV_PMU_RPC_ID_PERF_CHANGE_SEQ_QUERY 0x08U |
52 | #define NV_PMU_RPC_ID_PERF_PERF_LIMITS_INVALIDATE 0x09 | 52 | #define NV_PMU_RPC_ID_PERF_PERF_LIMITS_INVALIDATE 0x09U |
53 | #define NV_PMU_RPC_ID_PERF_VFE_EQU_EVAL 0x0A | 53 | #define NV_PMU_RPC_ID_PERF_VFE_EQU_EVAL 0x0AU |
54 | #define NV_PMU_RPC_ID_PERF_VFE_INVALIDATE 0x0B | 54 | #define NV_PMU_RPC_ID_PERF_VFE_INVALIDATE 0x0BU |
55 | #define NV_PMU_RPC_ID_PERF_VFE_EQU_MONITOR_SET 0x0C | 55 | #define NV_PMU_RPC_ID_PERF_VFE_EQU_MONITOR_SET 0x0CU |
56 | #define NV_PMU_RPC_ID_PERF_VFE_EQU_MONITOR_GET 0x0D | 56 | #define NV_PMU_RPC_ID_PERF_VFE_EQU_MONITOR_GET 0x0DU |
57 | #define NV_PMU_RPC_ID_PERF__COUNT 0x0E | 57 | #define NV_PMU_RPC_ID_PERF__COUNT 0x0EU |
58 | /* | 58 | /* |
59 | * Defines the structure that holds data | 59 | * Defines the structure that holds data |
60 | * used to execute LOAD RPC. | 60 | * used to execute LOAD RPC. |
@@ -76,7 +76,7 @@ struct nv_pmu_perf_cmd_set_object { | |||
76 | (offsetof(struct nv_pmu_perf_cmd_set_object, object)) | 76 | (offsetof(struct nv_pmu_perf_cmd_set_object, object)) |
77 | 77 | ||
78 | /* RPC IDs */ | 78 | /* RPC IDs */ |
79 | #define NV_PMU_PERF_RPC_ID_VFE_LOAD (0x00000001) | 79 | #define NV_PMU_PERF_RPC_ID_VFE_LOAD (0x00000001U) |
80 | 80 | ||
81 | /*! | 81 | /*! |
82 | * Command requesting execution of the perf RPC. | 82 | * Command requesting execution of the perf RPC. |
@@ -121,10 +121,10 @@ struct nv_pmu_perf_rpc { | |||
121 | 121 | ||
122 | 122 | ||
123 | /* PERF Message-type Definitions */ | 123 | /* PERF Message-type Definitions */ |
124 | #define NV_PMU_PERF_MSG_ID_RPC (0x00000003) | 124 | #define NV_PMU_PERF_MSG_ID_RPC (0x00000003U) |
125 | #define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_SET (0x00000004) | 125 | #define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_SET (0x00000004U) |
126 | #define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000006) | 126 | #define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000006U) |
127 | #define NV_PMU_PERF_MSG_ID_VFE_CALLBACK (0x00000005) | 127 | #define NV_PMU_PERF_MSG_ID_VFE_CALLBACK (0x00000005U) |
128 | 128 | ||
129 | /*! | 129 | /*! |
130 | * Message carrying the result of the perf RPC execution. | 130 | * Message carrying the result of the perf RPC execution. |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifpmgr.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifpmgr.h index 83f9ac1e..a0e6c82c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifpmgr.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifpmgr.h | |||
@@ -35,7 +35,7 @@ struct nv_pmu_pmgr_i2c_device_desc { | |||
35 | u8 i2c_port; | 35 | u8 i2c_port; |
36 | }; | 36 | }; |
37 | 37 | ||
38 | #define NV_PMU_PMGR_I2C_DEVICE_DESC_TABLE_MAX_DEVICES (32) | 38 | #define NV_PMU_PMGR_I2C_DEVICE_DESC_TABLE_MAX_DEVICES (32U) |
39 | 39 | ||
40 | struct nv_pmu_pmgr_i2c_device_desc_table { | 40 | struct nv_pmu_pmgr_i2c_device_desc_table { |
41 | u32 dev_mask; | 41 | u32 dev_mask; |
@@ -48,7 +48,7 @@ struct nv_pmu_pmgr_pwr_device_desc { | |||
48 | u32 power_corr_factor; | 48 | u32 power_corr_factor; |
49 | }; | 49 | }; |
50 | 50 | ||
51 | #define NV_PMU_PMGR_PWR_DEVICE_INA3221_CH_NUM 0x03 | 51 | #define NV_PMU_PMGR_PWR_DEVICE_INA3221_CH_NUM 0x03U |
52 | 52 | ||
53 | struct nv_pmu_pmgr_pwr_device_desc_ina3221 { | 53 | struct nv_pmu_pmgr_pwr_device_desc_ina3221 { |
54 | struct nv_pmu_pmgr_pwr_device_desc super; | 54 | struct nv_pmu_pmgr_pwr_device_desc super; |
@@ -105,9 +105,9 @@ struct nv_pmu_pmgr_pwr_channel { | |||
105 | u32 dependent_ch_mask; | 105 | u32 dependent_ch_mask; |
106 | }; | 106 | }; |
107 | 107 | ||
108 | #define NV_PMU_PMGR_PWR_CHANNEL_MAX_CHANNELS 16 | 108 | #define NV_PMU_PMGR_PWR_CHANNEL_MAX_CHANNELS 16U |
109 | 109 | ||
110 | #define NV_PMU_PMGR_PWR_CHANNEL_MAX_CHRELATIONSHIPS 16 | 110 | #define NV_PMU_PMGR_PWR_CHANNEL_MAX_CHRELATIONSHIPS 16U |
111 | 111 | ||
112 | struct nv_pmu_pmgr_pwr_channel_sensor { | 112 | struct nv_pmu_pmgr_pwr_channel_sensor { |
113 | struct nv_pmu_pmgr_pwr_channel super; | 113 | struct nv_pmu_pmgr_pwr_channel super; |
@@ -126,7 +126,7 @@ union nv_pmu_pmgr_pwr_channel_union { | |||
126 | struct nv_pmu_pmgr_pwr_channel_pmu_compactible pmu_pwr_channel; | 126 | struct nv_pmu_pmgr_pwr_channel_pmu_compactible pmu_pwr_channel; |
127 | }; | 127 | }; |
128 | 128 | ||
129 | #define NV_PMU_PMGR_PWR_MONITOR_TYPE_NO_POLLING 0x02 | 129 | #define NV_PMU_PMGR_PWR_MONITOR_TYPE_NO_POLLING 0x02U |
130 | 130 | ||
131 | struct nv_pmu_pmgr_pwr_monitor_pstate { | 131 | struct nv_pmu_pmgr_pwr_monitor_pstate { |
132 | u32 hw_channel_mask; | 132 | u32 hw_channel_mask; |
@@ -193,9 +193,9 @@ struct nv_pmu_pmgr_pwr_monitor_pack { | |||
193 | struct nv_pmu_pmgr_pwr_chrelationship_desc ch_rels; | 193 | struct nv_pmu_pmgr_pwr_chrelationship_desc ch_rels; |
194 | }; | 194 | }; |
195 | 195 | ||
196 | #define NV_PMU_PMGR_PWR_POLICY_MAX_POLICIES 32 | 196 | #define NV_PMU_PMGR_PWR_POLICY_MAX_POLICIES 32U |
197 | 197 | ||
198 | #define NV_PMU_PMGR_PWR_POLICY_MAX_POLICY_RELATIONSHIPS 32 | 198 | #define NV_PMU_PMGR_PWR_POLICY_MAX_POLICY_RELATIONSHIPS 32U |
199 | 199 | ||
200 | struct nv_pmu_pmgr_pwr_policy { | 200 | struct nv_pmu_pmgr_pwr_policy { |
201 | struct nv_pmu_boardobj super; | 201 | struct nv_pmu_boardobj super; |
@@ -258,21 +258,21 @@ union nv_pmu_pmgr_pwr_violation_union { | |||
258 | struct nv_pmu_pmgr_pwr_violation_pmu_compactible violation; | 258 | struct nv_pmu_pmgr_pwr_violation_pmu_compactible violation; |
259 | }; | 259 | }; |
260 | 260 | ||
261 | #define NV_PMU_PMGR_PWR_POLICY_DESC_TABLE_VERSION_3X 0x30 | 261 | #define NV_PMU_PMGR_PWR_POLICY_DESC_TABLE_VERSION_3X 0x30U |
262 | 262 | ||
263 | NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_policy_union, | 263 | NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_policy_union, |
264 | sizeof(union nv_pmu_pmgr_pwr_policy_union)); | 264 | sizeof(union nv_pmu_pmgr_pwr_policy_union)); |
265 | NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_policy_relationship_union, | 265 | NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_policy_relationship_union, |
266 | sizeof(union nv_pmu_pmgr_pwr_policy_relationship_union)); | 266 | sizeof(union nv_pmu_pmgr_pwr_policy_relationship_union)); |
267 | 267 | ||
268 | #define NV_PMU_PERF_DOMAIN_GROUP_MAX_GROUPS 2 | 268 | #define NV_PMU_PERF_DOMAIN_GROUP_MAX_GROUPS 2U |
269 | 269 | ||
270 | struct nv_pmu_perf_domain_group_limits | 270 | struct nv_pmu_perf_domain_group_limits |
271 | { | 271 | { |
272 | u32 values[NV_PMU_PERF_DOMAIN_GROUP_MAX_GROUPS]; | 272 | u32 values[NV_PMU_PERF_DOMAIN_GROUP_MAX_GROUPS]; |
273 | } ; | 273 | } ; |
274 | 274 | ||
275 | #define NV_PMU_PMGR_RESERVED_PWR_POLICY_MASK_COUNT 0x6 | 275 | #define NV_PMU_PMGR_RESERVED_PWR_POLICY_MASK_COUNT 0x6U |
276 | 276 | ||
277 | struct nv_pmu_pmgr_pwr_policy_desc_header { | 277 | struct nv_pmu_pmgr_pwr_policy_desc_header { |
278 | struct nv_pmu_boardobjgrp_e32 super; | 278 | struct nv_pmu_boardobjgrp_e32 super; |
@@ -338,15 +338,15 @@ struct nv_pmu_pmgr_pwr_policy_pack { | |||
338 | struct nv_pmu_pmgr_pwr_violation_desc violations; | 338 | struct nv_pmu_pmgr_pwr_violation_desc violations; |
339 | }; | 339 | }; |
340 | 340 | ||
341 | #define NV_PMU_PMGR_CMD_ID_SET_OBJECT (0x00000000) | 341 | #define NV_PMU_PMGR_CMD_ID_SET_OBJECT (0x00000000U) |
342 | 342 | ||
343 | #define NV_PMU_PMGR_MSG_ID_QUERY (0x00000002) | 343 | #define NV_PMU_PMGR_MSG_ID_QUERY (0x00000002U) |
344 | 344 | ||
345 | #define NV_PMU_PMGR_CMD_ID_PWR_DEVICES_QUERY (0x00000001) | 345 | #define NV_PMU_PMGR_CMD_ID_PWR_DEVICES_QUERY (0x00000001U) |
346 | 346 | ||
347 | #define NV_PMU_PMGR_CMD_ID_LOAD (0x00000006) | 347 | #define NV_PMU_PMGR_CMD_ID_LOAD (0x00000006U) |
348 | 348 | ||
349 | #define NV_PMU_PMGR_CMD_ID_UNLOAD (0x00000007) | 349 | #define NV_PMU_PMGR_CMD_ID_UNLOAD (0x00000007U) |
350 | 350 | ||
351 | struct nv_pmu_pmgr_cmd_set_object { | 351 | struct nv_pmu_pmgr_cmd_set_object { |
352 | u8 cmd_type; | 352 | u8 cmd_type; |
@@ -355,15 +355,15 @@ struct nv_pmu_pmgr_cmd_set_object { | |||
355 | struct nv_pmu_allocation object; | 355 | struct nv_pmu_allocation object; |
356 | }; | 356 | }; |
357 | 357 | ||
358 | #define NV_PMU_PMGR_SET_OBJECT_ALLOC_OFFSET (0x04) | 358 | #define NV_PMU_PMGR_SET_OBJECT_ALLOC_OFFSET (0x04U) |
359 | 359 | ||
360 | #define NV_PMU_PMGR_OBJECT_I2C_DEVICE_DESC_TABLE (0x00000000) | 360 | #define NV_PMU_PMGR_OBJECT_I2C_DEVICE_DESC_TABLE (0x00000000U) |
361 | 361 | ||
362 | #define NV_PMU_PMGR_OBJECT_PWR_DEVICE_DESC_TABLE (0x00000001) | 362 | #define NV_PMU_PMGR_OBJECT_PWR_DEVICE_DESC_TABLE (0x00000001U) |
363 | 363 | ||
364 | #define NV_PMU_PMGR_OBJECT_PWR_MONITOR (0x00000002) | 364 | #define NV_PMU_PMGR_OBJECT_PWR_MONITOR (0x00000002U) |
365 | 365 | ||
366 | #define NV_PMU_PMGR_OBJECT_PWR_POLICY (0x00000005) | 366 | #define NV_PMU_PMGR_OBJECT_PWR_POLICY (0x00000005U) |
367 | 367 | ||
368 | struct nv_pmu_pmgr_pwr_devices_query_payload { | 368 | struct nv_pmu_pmgr_pwr_devices_query_payload { |
369 | struct { | 369 | struct { |
@@ -380,7 +380,7 @@ struct nv_pmu_pmgr_cmd_pwr_devices_query { | |||
380 | struct nv_pmu_allocation payload; | 380 | struct nv_pmu_allocation payload; |
381 | }; | 381 | }; |
382 | 382 | ||
383 | #define NV_PMU_PMGR_PWR_DEVICES_QUERY_ALLOC_OFFSET (0x08) | 383 | #define NV_PMU_PMGR_PWR_DEVICES_QUERY_ALLOC_OFFSET (0x08U) |
384 | 384 | ||
385 | struct nv_pmu_pmgr_cmd_load { | 385 | struct nv_pmu_pmgr_cmd_load { |
386 | u8 cmd_type; | 386 | u8 cmd_type; |
@@ -400,11 +400,11 @@ struct nv_pmu_pmgr_cmd { | |||
400 | }; | 400 | }; |
401 | }; | 401 | }; |
402 | 402 | ||
403 | #define NV_PMU_PMGR_MSG_ID_SET_OBJECT (0x00000000) | 403 | #define NV_PMU_PMGR_MSG_ID_SET_OBJECT (0x00000000U) |
404 | 404 | ||
405 | #define NV_PMU_PMGR_MSG_ID_LOAD (0x00000004) | 405 | #define NV_PMU_PMGR_MSG_ID_LOAD (0x00000004U) |
406 | 406 | ||
407 | #define NV_PMU_PMGR_MSG_ID_UNLOAD (0x00000005) | 407 | #define NV_PMU_PMGR_MSG_ID_UNLOAD (0x00000005U) |
408 | 408 | ||
409 | struct nv_pmu_pmgr_msg_set_object { | 409 | struct nv_pmu_pmgr_msg_set_object { |
410 | u8 msg_type; | 410 | u8 msg_type; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h index f2edd6c6..0161719a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h | |||
@@ -26,13 +26,13 @@ | |||
26 | #include <nvgpu/flcnif_cmn.h> | 26 | #include <nvgpu/flcnif_cmn.h> |
27 | #include "ctrl/ctrlvolt.h" | 27 | #include "ctrl/ctrlvolt.h" |
28 | 28 | ||
29 | #define NV_PMU_VOLT_VALUE_0V_IN_UV (0) | 29 | #define NV_PMU_VOLT_VALUE_0V_IN_UV (0U) |
30 | 30 | ||
31 | /* ------------- VOLT_RAIL's GRP_SET defines and structures ------------- */ | 31 | /* ------------- VOLT_RAIL's GRP_SET defines and structures ------------- */ |
32 | 32 | ||
33 | #define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_RAIL 0x00 | 33 | #define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_RAIL 0x00U |
34 | #define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_DEVICE 0x01 | 34 | #define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_DEVICE 0x01U |
35 | #define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_POLICY 0x02 | 35 | #define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_POLICY 0x02U |
36 | 36 | ||
37 | 37 | ||
38 | struct nv_pmu_volt_volt_rail_boardobjgrp_set_header { | 38 | struct nv_pmu_volt_volt_rail_boardobjgrp_set_header { |
@@ -264,17 +264,17 @@ struct nv_pmu_volt_volt_rail_set_noise_unaware_vmin { | |||
264 | rail_list; | 264 | rail_list; |
265 | }; | 265 | }; |
266 | 266 | ||
267 | #define NV_PMU_VOLT_CMD_ID_BOARDOBJ_GRP_SET (0x00000000) | 267 | #define NV_PMU_VOLT_CMD_ID_BOARDOBJ_GRP_SET (0x00000000U) |
268 | #define NV_PMU_VOLT_CMD_ID_RPC (0x00000001) | 268 | #define NV_PMU_VOLT_CMD_ID_RPC (0x00000001U) |
269 | #define NV_PMU_VOLT_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002) | 269 | #define NV_PMU_VOLT_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002U) |
270 | #define NV_PMU_VOLT_RPC_ID_VOLT_RAIL_SET_NOISE_UNAWARE_VMIN (0x00000004) | 270 | #define NV_PMU_VOLT_RPC_ID_VOLT_RAIL_SET_NOISE_UNAWARE_VMIN (0x00000004U) |
271 | 271 | ||
272 | /*! | 272 | /*! |
273 | * PMU VOLT RPC calls. | 273 | * PMU VOLT RPC calls. |
274 | */ | 274 | */ |
275 | #define NV_PMU_VOLT_RPC_ID_LOAD (0x00000000) | 275 | #define NV_PMU_VOLT_RPC_ID_LOAD (0x00000000U) |
276 | #define NV_PMU_VOLT_RPC_ID_VOLT_POLICY_SET_VOLTAGE (0x00000002) | 276 | #define NV_PMU_VOLT_RPC_ID_VOLT_POLICY_SET_VOLTAGE (0x00000002U) |
277 | #define NV_PMU_VOLT_RPC_ID_VOLT_RAIL_GET_VOLTAGE (0x00000003) | 277 | #define NV_PMU_VOLT_RPC_ID_VOLT_RAIL_GET_VOLTAGE (0x00000003U) |
278 | 278 | ||
279 | struct nv_pmu_volt_cmd_rpc { | 279 | struct nv_pmu_volt_cmd_rpc { |
280 | u8 cmd_type; | 280 | u8 cmd_type; |
@@ -310,9 +310,9 @@ struct nv_pmu_volt_rpc { | |||
310 | /*! | 310 | /*! |
311 | * VOLT MSG ID definitions | 311 | * VOLT MSG ID definitions |
312 | */ | 312 | */ |
313 | #define NV_PMU_VOLT_MSG_ID_BOARDOBJ_GRP_SET (0x00000000) | 313 | #define NV_PMU_VOLT_MSG_ID_BOARDOBJ_GRP_SET (0x00000000U) |
314 | #define NV_PMU_VOLT_MSG_ID_RPC (0x00000001) | 314 | #define NV_PMU_VOLT_MSG_ID_RPC (0x00000001U) |
315 | #define NV_PMU_VOLT_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002) | 315 | #define NV_PMU_VOLT_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002U) |
316 | 316 | ||
317 | /*! | 317 | /*! |
318 | * Message carrying the result of the VOLT RPC execution. | 318 | * Message carrying the result of the VOLT RPC execution. |
@@ -335,7 +335,7 @@ struct nv_pmu_volt_msg { | |||
335 | }; | 335 | }; |
336 | }; | 336 | }; |
337 | 337 | ||
338 | #define NV_PMU_VF_INJECT_MAX_VOLT_RAILS (2) | 338 | #define NV_PMU_VF_INJECT_MAX_VOLT_RAILS (2U) |
339 | 339 | ||
340 | struct nv_pmu_volt_volt_rail_list { | 340 | struct nv_pmu_volt_volt_rail_list { |
341 | u8 num_rails; | 341 | u8 num_rails; |
@@ -350,13 +350,13 @@ struct nv_pmu_volt_volt_rail_list_v1 { | |||
350 | }; | 350 | }; |
351 | 351 | ||
352 | /* VOLT RPC */ | 352 | /* VOLT RPC */ |
353 | #define NV_PMU_RPC_ID_VOLT_BOARD_OBJ_GRP_CMD 0x00 | 353 | #define NV_PMU_RPC_ID_VOLT_BOARD_OBJ_GRP_CMD 0x00U |
354 | #define NV_PMU_RPC_ID_VOLT_VOLT_SET_VOLTAGE 0x01 | 354 | #define NV_PMU_RPC_ID_VOLT_VOLT_SET_VOLTAGE 0x01U |
355 | #define NV_PMU_RPC_ID_VOLT_LOAD 0x02 | 355 | #define NV_PMU_RPC_ID_VOLT_LOAD 0x02U |
356 | #define NV_PMU_RPC_ID_VOLT_VOLT_RAIL_GET_VOLTAGE 0x03 | 356 | #define NV_PMU_RPC_ID_VOLT_VOLT_RAIL_GET_VOLTAGE 0x03U |
357 | #define NV_PMU_RPC_ID_VOLT_VOLT_POLICY_SANITY_CHECK 0x04 | 357 | #define NV_PMU_RPC_ID_VOLT_VOLT_POLICY_SANITY_CHECK 0x04U |
358 | #define NV_PMU_RPC_ID_VOLT_TEST_EXECUTE 0x05 | 358 | #define NV_PMU_RPC_ID_VOLT_TEST_EXECUTE 0x05U |
359 | #define NV_PMU_RPC_ID_VOLT__COUNT 0x06 | 359 | #define NV_PMU_RPC_ID_VOLT__COUNT 0x06U |
360 | 360 | ||
361 | /* | 361 | /* |
362 | * Defines the structure that holds data | 362 | * Defines the structure that holds data |