2 files changed, 0 insertions, 9 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index 27c2df3d..01537042 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -511,9 +511,6 @@ static u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
 
 static void gr_gm20b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
 {
-        tegra_clk_writel(CLK_RST_CONTROLLER_MISC_CLK_ENB_0_ALL_VISIBLE,
-                        CLK_RST_CONTROLLER_MISC_CLK_ENB_0);
-
 #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)
         tegra_fuse_writel(0x1, FUSE_FUSEBYPASS_0);
         tegra_fuse_writel(0x0, FUSE_WRITE_ACCESS_SW_0);
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
index fd24d105..84eb3862 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
@@ -28,12 +28,6 @@ enum {
         MAXWELL_CHANNEL_GPFIFO_A= 0xB06F,
 };
 
-#define tegra_clk_writel(value, offset) \
-        writel(value, IO_ADDRESS(0x60006000 + offset))
-
-#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0               0x48
-#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_ALL_VISIBLE   BIT(28)
-
 #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)
 #define FUSE_FUSEBYPASS_0                               0x24
 #define FUSE_WRITE_ACCESS_SW_0                          0x30