6 files changed, 67 insertions, 36 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c
index 18567064..4f33c78f 100644
--- a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c
@@ -313,33 +313,17 @@ static int nvgpu_gpu_ioctl_set_mmu_debug_mode(
                 struct gk20a *g,
                 struct nvgpu_gpu_mmu_debug_mode_args *args)
 {
-        int err = 0;
-        u32 reg_val, mmu_debug_ctrl;
-
-        err = gk20a_busy(g->dev);
-        if (err) {
+        if (gk20a_busy(g->dev)) {
                 gk20a_err(dev_from_gk20a(g), "failed to power on gpu\n");
                 return -EINVAL;
         }
 
         mutex_lock(&g->dbg_sessions_lock);
-
-        if (args->state == 1) {
-                mmu_debug_ctrl = fb_mmu_debug_ctrl_debug_enabled_f();
-                g->mmu_debug_ctrl = true;
-        } else {
-                mmu_debug_ctrl = fb_mmu_debug_ctrl_debug_disabled_f();
-                g->mmu_debug_ctrl = false;
-        }
-
-        reg_val = gk20a_readl(g, fb_mmu_debug_ctrl_r());
-        reg_val = set_field(reg_val,
-                                fb_mmu_debug_ctrl_debug_m(), mmu_debug_ctrl);
-        gk20a_writel(g, fb_mmu_debug_ctrl_r(), reg_val);
-
+        g->ops.mm.set_debug_mode(g, args->state == 1);
         mutex_unlock(&g->dbg_sessions_lock);
+
         gk20a_idle(g->dev);
-        return err;
+        return 0;
 }
 
 static int nvgpu_gpu_ioctl_set_debug_mode(
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c
index dfc7d34c..7ac600c0 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.c
@@ -747,21 +747,6 @@ static int gk20a_detect_chip(struct gk20a *g)
         return gpu_init_hal(g);
 }
 
-static void gk20a_pm_restore_debug_setting(struct gk20a *g)
-{
-        u32 mmu_debug_ctrl;
-
-        /* restore mmu debug state */
-        if (g->mmu_debug_ctrl)
-                mmu_debug_ctrl = fb_mmu_debug_ctrl_debug_enabled_v();
-        else
-                mmu_debug_ctrl = fb_mmu_debug_ctrl_debug_disabled_v();
-
-        mmu_debug_ctrl = gk20a_readl(g, fb_mmu_debug_ctrl_r());
-        mmu_debug_ctrl = set_field(mmu_debug_ctrl, fb_mmu_debug_ctrl_debug_m(), mmu_debug_ctrl);
-        gk20a_writel(g, fb_mmu_debug_ctrl_r(), mmu_debug_ctrl);
-}
-
 static int gk20a_pm_finalize_poweron(struct device *dev)
 {
         struct platform_device *pdev = to_platform_device(dev);
@@ -890,7 +875,7 @@ static int gk20a_pm_finalize_poweron(struct device *dev)
         }
 
         /* Restore the debug setting */
-        gk20a_pm_restore_debug_setting(g);
+        g->ops.mm.set_debug_mode(g, g->mmu_debug_ctrl);
 
         gk20a_channel_resume(g);
         set_user_nice(current, nice_value);
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index ff37039f..fe51f356 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -346,6 +346,7 @@ struct gpu_ops {
         struct {
                 bool (*support_sparse)(struct gk20a *g);
                 bool (*is_debug_mode_enabled)(struct gk20a *g);
+                void (*set_debug_mode)(struct gk20a *g, bool enable);
                 u64 (*gmmu_map)(struct vm_gk20a *vm,
                                 u64 map_offset,
                                 struct sg_table *sgt,
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
index 86b9f045..4c31d5e4 100644
--- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
@@ -3723,6 +3723,24 @@ bool gk20a_mm_mmu_debug_mode_enabled(struct gk20a *g)
                 fb_mmu_debug_ctrl_debug_enabled_v();
 }
 
+static void gk20a_mm_mmu_set_debug_mode(struct gk20a *g, bool enable)
+{
+        u32 reg_val, debug_ctrl;
+
+        reg_val = gk20a_readl(g, fb_mmu_debug_ctrl_r());
+        if (enable) {
+                debug_ctrl = fb_mmu_debug_ctrl_debug_enabled_f();
+                g->mmu_debug_ctrl = true;
+        } else {
+                debug_ctrl = fb_mmu_debug_ctrl_debug_disabled_f();
+                g->mmu_debug_ctrl = false;
+        }
+
+        reg_val = set_field(reg_val,
+                                fb_mmu_debug_ctrl_debug_m(), debug_ctrl);
+        gk20a_writel(g, fb_mmu_debug_ctrl_r(), reg_val);
+}
+
 u32 gk20a_mm_get_physical_addr_bits(struct gk20a *g)
 {
         return 34;
@@ -3769,6 +3787,7 @@ clean_up:
 void gk20a_init_mm(struct gpu_ops *gops)
 {
         gops->mm.is_debug_mode_enabled = gk20a_mm_mmu_debug_mode_enabled;
+        gops->mm.set_debug_mode = gk20a_mm_mmu_set_debug_mode;
         gops->mm.gmmu_map = gk20a_locked_gmmu_map;
         gops->mm.gmmu_unmap = gk20a_locked_gmmu_unmap;
         gops->mm.vm_remove = gk20a_vm_remove_support;
diff --git a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h
index a941eb59..4a712394 100644
--- a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h
@@ -3562,6 +3562,10 @@ static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void)
 {
         return 0x004188b0;
 }
+static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_m(void)
+{
+        return 0x1 << 16;
+}
 static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r)
 {
         return (r >> 16) & 0x1;
@@ -3570,6 +3574,18 @@ static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void)
 {
         return 0x00000001;
 }
+static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_f(void)
+{
+        return 0x10000;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_v(void)
+{
+        return 0x00000000;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_f(void)
+{
+        return 0x0;
+}
 static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void)
 {
         return 0x004188b4;
diff --git a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c
index 3d75a631..9fdd860b 100644
--- a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c
@@ -78,6 +78,31 @@ static bool gm20b_mm_mmu_debug_mode_enabled(struct gk20a *g)
                 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v();
 }
 
+static void gm20b_mm_mmu_set_debug_mode(struct gk20a *g, bool enable)
+{
+        u32 reg_val, fb_debug_ctrl, gpc_debug_ctrl;
+
+        if (enable) {
+                fb_debug_ctrl = fb_mmu_debug_ctrl_debug_enabled_f();
+                gpc_debug_ctrl = gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_f();
+                g->mmu_debug_ctrl = true;
+        } else {
+                fb_debug_ctrl = fb_mmu_debug_ctrl_debug_disabled_f();
+                gpc_debug_ctrl = gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_f();
+                g->mmu_debug_ctrl = false;
+        }
+
+        reg_val = gk20a_readl(g, fb_mmu_debug_ctrl_r());
+        reg_val = set_field(reg_val,
+                        fb_mmu_debug_ctrl_debug_m(), fb_debug_ctrl);
+        gk20a_writel(g, fb_mmu_debug_ctrl_r(), reg_val);
+
+        reg_val = gk20a_readl(g, gr_gpcs_pri_mmu_debug_ctrl_r());
+        reg_val = set_field(reg_val,
+                        gr_gpcs_pri_mmu_debug_ctrl_debug_m(), gpc_debug_ctrl);
+        gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(), reg_val);
+}
+
 static void gm20b_mm_set_big_page_size(struct gk20a *g,
                                 void *inst_ptr, int size)
 {
@@ -112,6 +137,7 @@ void gm20b_init_mm(struct gpu_ops *gops)
 {
         gops->mm.support_sparse = gm20b_mm_support_sparse;
         gops->mm.is_debug_mode_enabled = gm20b_mm_mmu_debug_mode_enabled;
+        gops->mm.set_debug_mode = gm20b_mm_mmu_set_debug_mode;
         gops->mm.gmmu_map = gk20a_locked_gmmu_map;
         gops->mm.gmmu_unmap = gk20a_locked_gmmu_unmap;
         gops->mm.vm_remove = gk20a_vm_remove_support;