diff options
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c | 15 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 4 |
5 files changed, 32 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 6959b86a..a76798d1 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -97,6 +97,7 @@ enum nvgpu_litter_value { | |||
97 | GPU_LIT_NUM_PES_PER_GPC, | 97 | GPU_LIT_NUM_PES_PER_GPC, |
98 | GPU_LIT_NUM_ZCULL_BANKS, | 98 | GPU_LIT_NUM_ZCULL_BANKS, |
99 | GPU_LIT_NUM_TPC_PER_GPC, | 99 | GPU_LIT_NUM_TPC_PER_GPC, |
100 | GPU_LIT_NUM_SM_PER_TPC, | ||
100 | GPU_LIT_NUM_FBPS, | 101 | GPU_LIT_NUM_FBPS, |
101 | GPU_LIT_GPC_BASE, | 102 | GPU_LIT_GPC_BASE, |
102 | GPU_LIT_GPC_STRIDE, | 103 | GPU_LIT_GPC_STRIDE, |
@@ -303,6 +304,7 @@ struct gpu_ops { | |||
303 | u32 gpc, u32 tpc, u32 smid); | 304 | u32 gpc, u32 tpc, u32 smid); |
304 | void (*program_active_tpc_counts)(struct gk20a *g, u32 gpc); | 305 | void (*program_active_tpc_counts)(struct gk20a *g, u32 gpc); |
305 | int (*setup_rop_mapping)(struct gk20a *g, struct gr_gk20a *gr); | 306 | int (*setup_rop_mapping)(struct gk20a *g, struct gr_gk20a *gr); |
307 | int (*init_sw_veid_bundle)(struct gk20a *g); | ||
306 | } gr; | 308 | } gr; |
307 | const char *name; | 309 | const char *name; |
308 | struct { | 310 | struct { |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c index 5a1152d5..f040ffc0 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c | |||
@@ -205,6 +205,15 @@ static int gr_gk20a_init_ctx_vars_fw(struct gk20a *g, struct gr_gk20a *gr) | |||
205 | if (err) | 205 | if (err) |
206 | goto clean_up; | 206 | goto clean_up; |
207 | break; | 207 | break; |
208 | case NETLIST_REGIONID_SWVEIDBUNDLEINIT: | ||
209 | gk20a_dbg_info( | ||
210 | "NETLIST_REGIONID_SW_VEID_BUNDLE_INIT"); | ||
211 | err = gr_gk20a_alloc_load_netlist_av( | ||
212 | src, size, | ||
213 | &g->gr.ctx_vars.sw_veid_bundle_init); | ||
214 | if (err) | ||
215 | goto clean_up; | ||
216 | break; | ||
208 | case NETLIST_REGIONID_CTXREG_SYS: | 217 | case NETLIST_REGIONID_CTXREG_SYS: |
209 | gk20a_dbg_info("NETLIST_REGIONID_CTXREG_SYS"); | 218 | gk20a_dbg_info("NETLIST_REGIONID_CTXREG_SYS"); |
210 | err = gr_gk20a_alloc_load_netlist_aiv( | 219 | err = gr_gk20a_alloc_load_netlist_aiv( |
@@ -394,6 +403,7 @@ clean_up: | |||
394 | kfree(g->gr.ctx_vars.sw_method_init.l); | 403 | kfree(g->gr.ctx_vars.sw_method_init.l); |
395 | kfree(g->gr.ctx_vars.sw_ctx_load.l); | 404 | kfree(g->gr.ctx_vars.sw_ctx_load.l); |
396 | kfree(g->gr.ctx_vars.sw_non_ctx_load.l); | 405 | kfree(g->gr.ctx_vars.sw_non_ctx_load.l); |
406 | kfree(g->gr.ctx_vars.sw_veid_bundle_init.l); | ||
397 | kfree(g->gr.ctx_vars.ctxsw_regs.sys.l); | 407 | kfree(g->gr.ctx_vars.ctxsw_regs.sys.l); |
398 | kfree(g->gr.ctx_vars.ctxsw_regs.gpc.l); | 408 | kfree(g->gr.ctx_vars.ctxsw_regs.gpc.l); |
399 | kfree(g->gr.ctx_vars.ctxsw_regs.tpc.l); | 409 | kfree(g->gr.ctx_vars.ctxsw_regs.tpc.l); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c index 9430ce7b..70787202 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c +++ b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c | |||
@@ -3,7 +3,7 @@ | |||
3 | * | 3 | * |
4 | * GK20A Graphics Context for Simulation | 4 | * GK20A Graphics Context for Simulation |
5 | * | 5 | * |
6 | * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. | 6 | * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved. |
7 | * | 7 | * |
8 | * This program is free software; you can redistribute it and/or modify it | 8 | * This program is free software; you can redistribute it and/or modify it |
9 | * under the terms and conditions of the GNU General Public License, | 9 | * under the terms and conditions of the GNU General Public License, |
@@ -50,7 +50,8 @@ int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr) | |||
50 | &g->gr.ctx_vars.sw_method_init.count); | 50 | &g->gr.ctx_vars.sw_method_init.count); |
51 | gk20a_sim_esc_readl(g, "GRCTX_SW_CTX_LOAD_SIZE", 0, | 51 | gk20a_sim_esc_readl(g, "GRCTX_SW_CTX_LOAD_SIZE", 0, |
52 | &g->gr.ctx_vars.sw_ctx_load.count); | 52 | &g->gr.ctx_vars.sw_ctx_load.count); |
53 | 53 | gk20a_sim_esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT_SIZE", 0, | |
54 | &g->gr.ctx_vars.sw_veid_bundle_init.count); | ||
54 | 55 | ||
55 | gk20a_sim_esc_readl(g, "GRCTX_NONCTXSW_REG_SIZE", 0, | 56 | gk20a_sim_esc_readl(g, "GRCTX_NONCTXSW_REG_SIZE", 0, |
56 | &g->gr.ctx_vars.sw_non_ctx_load.count); | 57 | &g->gr.ctx_vars.sw_non_ctx_load.count); |
@@ -77,6 +78,7 @@ int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr) | |||
77 | err |= !alloc_av_list_gk20a(&g->gr.ctx_vars.sw_method_init); | 78 | err |= !alloc_av_list_gk20a(&g->gr.ctx_vars.sw_method_init); |
78 | err |= !alloc_aiv_list_gk20a(&g->gr.ctx_vars.sw_ctx_load); | 79 | err |= !alloc_aiv_list_gk20a(&g->gr.ctx_vars.sw_ctx_load); |
79 | err |= !alloc_av_list_gk20a(&g->gr.ctx_vars.sw_non_ctx_load); | 80 | err |= !alloc_av_list_gk20a(&g->gr.ctx_vars.sw_non_ctx_load); |
81 | err |= !alloc_av_list_gk20a(&g->gr.ctx_vars.sw_veid_bundle_init); | ||
80 | err |= !alloc_aiv_list_gk20a(&g->gr.ctx_vars.ctxsw_regs.sys); | 82 | err |= !alloc_aiv_list_gk20a(&g->gr.ctx_vars.ctxsw_regs.sys); |
81 | err |= !alloc_aiv_list_gk20a(&g->gr.ctx_vars.ctxsw_regs.gpc); | 83 | err |= !alloc_aiv_list_gk20a(&g->gr.ctx_vars.ctxsw_regs.gpc); |
82 | err |= !alloc_aiv_list_gk20a(&g->gr.ctx_vars.ctxsw_regs.tpc); | 84 | err |= !alloc_aiv_list_gk20a(&g->gr.ctx_vars.ctxsw_regs.tpc); |
@@ -139,6 +141,15 @@ int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr) | |||
139 | i, &l[i].value); | 141 | i, &l[i].value); |
140 | } | 142 | } |
141 | 143 | ||
144 | for (i = 0; i < g->gr.ctx_vars.sw_veid_bundle_init.count; i++) { | ||
145 | struct av_gk20a *l = g->gr.ctx_vars.sw_veid_bundle_init.l; | ||
146 | |||
147 | gk20a_sim_esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT:ADDR", | ||
148 | i, &l[i].addr); | ||
149 | gk20a_sim_esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT:VALUE", | ||
150 | i, &l[i].value); | ||
151 | } | ||
152 | |||
142 | for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.sys.count; i++) { | 153 | for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.sys.count; i++) { |
143 | struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.sys.l; | 154 | struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.sys.l; |
144 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_SYS:ADDR", | 155 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_SYS:ADDR", |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index e78c40f3..75f4379d 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -368,7 +368,7 @@ int gr_gk20a_wait_idle(struct gk20a *g, unsigned long end_jiffies, | |||
368 | return -EAGAIN; | 368 | return -EAGAIN; |
369 | } | 369 | } |
370 | 370 | ||
371 | static int gr_gk20a_wait_fe_idle(struct gk20a *g, unsigned long end_jiffies, | 371 | int gr_gk20a_wait_fe_idle(struct gk20a *g, unsigned long end_jiffies, |
372 | u32 expect_delay) | 372 | u32 expect_delay) |
373 | { | 373 | { |
374 | u32 val; | 374 | u32 val; |
@@ -1462,6 +1462,8 @@ static u32 gk20a_init_sw_bundle(struct gk20a *g) | |||
1462 | if (err) | 1462 | if (err) |
1463 | break; | 1463 | break; |
1464 | } | 1464 | } |
1465 | if (g->ops.gr.init_sw_veid_bundle) | ||
1466 | g->ops.gr.init_sw_veid_bundle(g); | ||
1465 | 1467 | ||
1466 | /* disable pipe mode override */ | 1468 | /* disable pipe mode override */ |
1467 | gk20a_writel(g, gr_pipe_bundle_config_r(), | 1469 | gk20a_writel(g, gr_pipe_bundle_config_r(), |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index c337a74a..df6a3f3c 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -231,6 +231,7 @@ struct gr_gk20a { | |||
231 | struct av_list_gk20a sw_method_init; | 231 | struct av_list_gk20a sw_method_init; |
232 | struct aiv_list_gk20a sw_ctx_load; | 232 | struct aiv_list_gk20a sw_ctx_load; |
233 | struct av_list_gk20a sw_non_ctx_load; | 233 | struct av_list_gk20a sw_non_ctx_load; |
234 | struct av_list_gk20a sw_veid_bundle_init; | ||
234 | struct { | 235 | struct { |
235 | struct aiv_list_gk20a sys; | 236 | struct aiv_list_gk20a sys; |
236 | struct aiv_list_gk20a gpc; | 237 | struct aiv_list_gk20a gpc; |
@@ -643,6 +644,9 @@ int gr_gk20a_get_ctx_id(struct gk20a *g, | |||
643 | 644 | ||
644 | u32 gk20a_mask_hww_warp_esr(u32 hww_warp_esr); | 645 | u32 gk20a_mask_hww_warp_esr(u32 hww_warp_esr); |
645 | 646 | ||
647 | int gr_gk20a_wait_fe_idle(struct gk20a *g, unsigned long end_jiffies, | ||
648 | u32 expect_delay); | ||
649 | |||
646 | bool gr_gk20a_suspend_context(struct channel_gk20a *ch); | 650 | bool gr_gk20a_suspend_context(struct channel_gk20a *ch); |
647 | bool gr_gk20a_resume_context(struct channel_gk20a *ch); | 651 | bool gr_gk20a_resume_context(struct channel_gk20a *ch); |
648 | int gr_gk20a_suspend_contexts(struct gk20a *g, | 652 | int gr_gk20a_suspend_contexts(struct gk20a *g, |