9 files changed, 31 insertions, 31 deletions

diff --git a/drivers/gpu/nvgpu/common/bus/bus_gk20a.c b/drivers/gpu/nvgpu/common/bus/bus_gk20a.c
index 5a424a50..5178dcd0 100644
--- a/drivers/gpu/nvgpu/common/bus/bus_gk20a.c
+++ b/drivers/gpu/nvgpu/common/bus/bus_gk20a.c
@@ -85,7 +85,7 @@ u32 gk20a_bus_set_bar0_window(struct gk20a *g, struct nvgpu_mem *mem,
 
         if (g->mm.pramin_window != win) {
                 gk20a_writel(g, bus_bar0_window_r(), win);
-                gk20a_readl(g, bus_bar0_window_r());
+                (void) gk20a_readl(g, bus_bar0_window_r());
                 g->mm.pramin_window = win;
         }
 
diff --git a/drivers/gpu/nvgpu/common/pramin.c b/drivers/gpu/nvgpu/common/pramin.c
index 1448fed1..26bf1038 100644
--- a/drivers/gpu/nvgpu/common/pramin.c
+++ b/drivers/gpu/nvgpu/common/pramin.c
@@ -82,7 +82,7 @@ static void nvgpu_pramin_access_batched(struct gk20a *g, struct nvgpu_mem *mem,
                 loop(g, start_reg, n / sizeof(u32), arg);
 
                 /* read back to synchronize accesses */
-                gk20a_readl(g, start_reg);
+                (void) gk20a_readl(g, start_reg);
 
                 nvgpu_spinlock_release(&g->mm.pramin_window_lock);
 
diff --git a/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gm20b.c b/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gm20b.c
index 24c35576..41a5391d 100644
--- a/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gm20b.c
+++ b/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gm20b.c
@@ -52,7 +52,7 @@ void gm20b_priv_ring_enable(struct gk20a *g)
 
         gk20a_writel(g, pri_ringstation_sys_decode_config_r(),
                         0x2);
-        gk20a_readl(g, pri_ringstation_sys_decode_config_r());
+        (void) gk20a_readl(g, pri_ringstation_sys_decode_config_r());
 }
 
 void gm20b_priv_ring_isr(struct gk20a *g)
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 91ffbb7e..a40d93fd 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -345,7 +345,7 @@ int gr_gk20a_wait_idle(struct gk20a *g, unsigned long duration_ms,
         do {
                 /* fmodel: host gets fifo_engine_status(gr) from gr
                    only when gr_status is read */
-                gk20a_readl(g, gr_status_r());
+                (void) gk20a_readl(g, gr_status_r());
 
                 gr_enabled = gk20a_readl(g, mc_enable_r()) &
                         mc_enable_pgraph_enabled_f();
@@ -1482,7 +1482,7 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g,
                         gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f() |
                         gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f() |
                         gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f());
-        gk20a_readl(g, gr_fecs_ctxsw_reset_ctl_r());
+        (void) gk20a_readl(g, gr_fecs_ctxsw_reset_ctl_r());
         nvgpu_udelay(10);
 
         gk20a_writel(g, gr_fecs_ctxsw_reset_ctl_r(),
@@ -1495,7 +1495,7 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g,
                         gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f() |
                         gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f() |
                         gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f());
-        gk20a_readl(g, gr_fecs_ctxsw_reset_ctl_r());
+        (void) gk20a_readl(g, gr_fecs_ctxsw_reset_ctl_r());
         nvgpu_udelay(10);
 
         if (!nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
index f7631a9c..f9996e71 100644
--- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
@@ -172,7 +172,7 @@ void mc_gk20a_intr_stall_pause(struct gk20a *g)
                 mc_intr_en_0_inta_disabled_f());
 
         /* flush previous write */
-        gk20a_readl(g, mc_intr_en_0_r());
+        (void) gk20a_readl(g, mc_intr_en_0_r());
 }
 
 void mc_gk20a_intr_stall_resume(struct gk20a *g)
@@ -181,7 +181,7 @@ void mc_gk20a_intr_stall_resume(struct gk20a *g)
                 mc_intr_en_0_inta_hardware_f());
 
         /* flush previous write */
-        gk20a_readl(g, mc_intr_en_0_r());
+        (void) gk20a_readl(g, mc_intr_en_0_r());
 }
 
 void mc_gk20a_intr_nonstall_pause(struct gk20a *g)
@@ -190,7 +190,7 @@ void mc_gk20a_intr_nonstall_pause(struct gk20a *g)
                 mc_intr_en_0_inta_disabled_f());
 
         /* flush previous write */
-        gk20a_readl(g, mc_intr_en_1_r());
+        (void) gk20a_readl(g, mc_intr_en_1_r());
 }
 
 void mc_gk20a_intr_nonstall_resume(struct gk20a *g)
@@ -199,7 +199,7 @@ void mc_gk20a_intr_nonstall_resume(struct gk20a *g)
                 mc_intr_en_0_inta_hardware_f());
 
         /* flush previous write */
-        gk20a_readl(g, mc_intr_en_1_r());
+        (void) gk20a_readl(g, mc_intr_en_1_r());
 }
 
 u32 mc_gk20a_intr_stall(struct gk20a *g)
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
index 03fed222..d2260d9c 100644
--- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
@@ -522,7 +522,7 @@ static int clk_enbale_pll_dvfs(struct gk20a *g)
         data = set_field(data, trim_sys_gpcpll_cfg_iddq_m(),
                          trim_sys_gpcpll_cfg_iddq_power_on_v());
         gk20a_writel(g, trim_sys_gpcpll_cfg_r(), data);
-        gk20a_readl(g, trim_sys_gpcpll_cfg_r());
+        (void) gk20a_readl(g, trim_sys_gpcpll_cfg_r());
         nvgpu_udelay(delay);
 
         /*
@@ -710,7 +710,7 @@ static int clk_slide_gpc_pll(struct gk20a *g, struct pll *gpll)
                         trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(),
                         trim_sys_gpcpll_ndiv_slowdown_en_dynramp_no_f());
         gk20a_writel(g, trim_sys_gpcpll_ndiv_slowdown_r(), data);
-        gk20a_readl(g, trim_sys_gpcpll_ndiv_slowdown_r());
+        (void) gk20a_readl(g, trim_sys_gpcpll_ndiv_slowdown_r());
 
         if (ramp_timeout <= 0) {
                 nvgpu_err(g, "gpcpll dynamic ramp timeout");
@@ -782,20 +782,20 @@ static int clk_lock_gpc_pll_under_bypass(struct gk20a *g, struct pll *gpll)
                 cfg = set_field(cfg, trim_sys_gpcpll_cfg_iddq_m(),
                                 trim_sys_gpcpll_cfg_iddq_power_on_v());
                 gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg);
-                gk20a_readl(g, trim_sys_gpcpll_cfg_r());
+                (void) gk20a_readl(g, trim_sys_gpcpll_cfg_r());
                 nvgpu_udelay(gpc_pll_params.iddq_exit_delay);
         } else {
                 /* clear SYNC_MODE before disabling PLL */
                 cfg = set_field(cfg, trim_sys_gpcpll_cfg_sync_mode_m(),
                                 trim_sys_gpcpll_cfg_sync_mode_disable_f());
                 gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg);
-                gk20a_readl(g, trim_sys_gpcpll_cfg_r());
+                (void) gk20a_readl(g, trim_sys_gpcpll_cfg_r());
 
                 /* disable running PLL before changing coefficients */
                 cfg = set_field(cfg, trim_sys_gpcpll_cfg_enable_m(),
                                 trim_sys_gpcpll_cfg_enable_no_f());
                 gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg);
-                gk20a_readl(g, trim_sys_gpcpll_cfg_r());
+                (void) gk20a_readl(g, trim_sys_gpcpll_cfg_r());
         }
 
         /* change coefficients */
@@ -826,7 +826,7 @@ static int clk_lock_gpc_pll_under_bypass(struct gk20a *g, struct pll *gpll)
 
         /* just delay in DVFS mode (lock cannot be used) */
         if (gpll->mode == GPC_PLL_MODE_DVFS) {
-                gk20a_readl(g, trim_sys_gpcpll_cfg_r());
+                (void) gk20a_readl(g, trim_sys_gpcpll_cfg_r());
                 nvgpu_udelay(gpc_pll_params.na_lock_delay);
                 gk20a_dbg_clk(g, "NA config_pll under bypass: %u (%u) kHz %d mV",
                               gpll->freq, gpll->freq / 2,
@@ -869,7 +869,7 @@ pll_locked:
         cfg = set_field(cfg, trim_sys_gpcpll_cfg_sync_mode_m(),
                         trim_sys_gpcpll_cfg_sync_mode_enable_f());
         gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg);
-        gk20a_readl(g, trim_sys_gpcpll_cfg_r());
+        (void) gk20a_readl(g, trim_sys_gpcpll_cfg_r());
 
         /* put PLL back on vco */
         throt = throttle_disable(g);
@@ -950,7 +950,7 @@ static int clk_program_gpc_pll(struct gk20a *g, struct pll *gpll_new,
                 gk20a_writel(g, trim_sys_gpc2clk_out_r(), data);
                 /* Intentional 2nd write to assure linear divider operation */
                 gk20a_writel(g, trim_sys_gpc2clk_out_r(), data);
-                gk20a_readl(g, trim_sys_gpc2clk_out_r());
+                (void) gk20a_readl(g, trim_sys_gpc2clk_out_r());
                 nvgpu_udelay(2);
         }
 
@@ -1013,7 +1013,7 @@ set_pldiv:
                 gk20a_writel(g, trim_sys_gpc2clk_out_r(), data);
                 /* Intentional 2nd write to assure linear divider operation */
                 gk20a_writel(g, trim_sys_gpc2clk_out_r(), data);
-                gk20a_readl(g, trim_sys_gpc2clk_out_r());
+                (void) gk20a_readl(g, trim_sys_gpc2clk_out_r());
         }
 
         /* slide up to target NDIV */
@@ -1178,7 +1178,7 @@ static int clk_disable_gpcpll(struct gk20a *g, int allow_slide)
         cfg = set_field(cfg, trim_sys_gpcpll_cfg_enable_m(),
                         trim_sys_gpcpll_cfg_enable_no_f());
         gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg);
-        gk20a_readl(g, trim_sys_gpcpll_cfg_r());
+        (void) gk20a_readl(g, trim_sys_gpcpll_cfg_r());
 
         clk->gpc_pll.enabled = false;
         clk->gpc_pll_last.enabled = false;
@@ -1397,7 +1397,7 @@ static int gm20b_init_clk_setup_hw(struct gk20a *g)
         data = set_field(data, therm_clk_slowdown_idle_factor_m(),
                          therm_clk_slowdown_idle_factor_disabled_f());
         gk20a_writel(g, therm_clk_slowdown_r(0), data);
-        gk20a_readl(g, therm_clk_slowdown_r(0));
+        (void) gk20a_readl(g, therm_clk_slowdown_r(0));
 
         if (g->clk.gpc_pll.mode == GPC_PLL_MODE_DVFS) {
                 return clk_enbale_pll_dvfs(g);
@@ -1565,7 +1565,7 @@ int gm20b_clk_get_gpcclk_clock_counter(struct clk_gk20a *clk, u64 *val)
                                  therm_clk_slowdown_idle_factor_m(),
                                  therm_clk_slowdown_idle_factor_disabled_f());
         gk20a_writel(g, therm_clk_slowdown_r(0), clk_slowdown);
-        gk20a_readl(g, therm_clk_slowdown_r(0));
+        (void) gk20a_readl(g, therm_clk_slowdown_r(0));
 
         gk20a_writel(g, trim_gpc_clk_cntr_ncgpcclk_cfg_r(0),
                      trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f());
@@ -1578,7 +1578,7 @@ int gm20b_clk_get_gpcclk_clock_counter(struct clk_gk20a *clk, u64 *val)
         /* It should take less than 25us to finish 800 cycle of 38.4MHz.
          *  But longer than 100us delay is required here.
          */
-        gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cfg_r(0));
+        (void) gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cfg_r(0));
         nvgpu_udelay(200);
 
         count1 = gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cnt_r(0));
diff --git a/drivers/gpu/nvgpu/gp106/clk_gp106.c b/drivers/gpu/nvgpu/gp106/clk_gp106.c
index 13a401f0..e892ceda 100644
--- a/drivers/gpu/nvgpu/gp106/clk_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/clk_gp106.c
@@ -188,7 +188,7 @@ u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c)
                                  trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_deasserted_f());
 
         /* Force wb() */
-        gk20a_readl(g, c->cntr.reg_ctrl_addr);
+        (void) gk20a_readl(g, c->cntr.reg_ctrl_addr);
 
         /* Wait for reset to happen */
         retries = CLK_DEFAULT_CNTRL_SETTLE_RETRIES;
@@ -209,7 +209,7 @@ u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c)
                                         trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_asserted_f()         |
                                         trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_f(XTAL_CNTR_CLKS)  |
                                         c->cntr.reg_ctrl_idx);
-        gk20a_readl(g, c->cntr.reg_ctrl_addr);
+        (void) gk20a_readl(g, c->cntr.reg_ctrl_addr);
 
         nvgpu_udelay(XTAL_CNTR_DELAY);
 
@@ -220,9 +220,9 @@ read_err:
         gk20a_writel(g, c->cntr.reg_ctrl_addr,
                                  trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_asserted_f() |
                                  trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_deasserted_f());
-        gk20a_readl(g, c->cntr.reg_ctrl_addr);
+        (void) gk20a_readl(g, c->cntr.reg_ctrl_addr);
         gk20a_writel(g, c->cntr.reg_ctrl_addr, save_reg);
-        gk20a_readl(g, c->cntr.reg_ctrl_addr);
+        (void) gk20a_readl(g, c->cntr.reg_ctrl_addr);
         nvgpu_mutex_release(&clk->clk_mutex);
 
         return cntr;
diff --git a/drivers/gpu/nvgpu/gp106/mclk_gp106.c b/drivers/gpu/nvgpu/gp106/mclk_gp106.c
index 36092a1a..6a49e83b 100644
--- a/drivers/gpu/nvgpu/gp106/mclk_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/mclk_gp106.c
@@ -3371,8 +3371,8 @@ int gp106_mclk_change(struct gk20a *g, u16 val)
         if (speed == GP106_MCLK_HIGH_SPEED) {
                 gk20a_writel(g, 0x132000, 0x98010000);
                 /* Introduce delay */
-                gk20a_readl(g, 0x132000);
-                gk20a_readl(g, 0x132000);
+                (void) gk20a_readl(g, 0x132000);
+                (void) gk20a_readl(g, 0x132000);
         }
 
         gk20a_writel(g, 0x137300, 0x20000103);
diff --git a/drivers/gpu/nvgpu/gp106/pmu_gp106.c b/drivers/gpu/nvgpu/gp106/pmu_gp106.c
index 963668c4..031ac7d8 100644
--- a/drivers/gpu/nvgpu/gp106/pmu_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/pmu_gp106.c
@@ -71,11 +71,11 @@ int gp106_pmu_engine_reset(struct gk20a *g, bool do_reset)
         if (do_reset) {
                 gk20a_writel(g, pwr_falcon_engine_r(),
                         pwr_falcon_engine_reset_false_f());
-                gk20a_readl(g, pwr_falcon_engine_r());
+                (void) gk20a_readl(g, pwr_falcon_engine_r());
         } else {
                 gk20a_writel(g, pwr_falcon_engine_r(),
                         pwr_falcon_engine_reset_true_f());
-                gk20a_readl(g, pwr_falcon_engine_r());
+                (void) gk20a_readl(g, pwr_falcon_engine_r());
         }
 
         return 0;