diff options
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/ce_gv11b.c | 16 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/ce_gv11b.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h | 10 |
6 files changed, 34 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c index 9dcba25a..2a40b089 100644 --- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GK20A Graphics Copy Engine (gr host) | 2 | * GK20A Graphics Copy Engine (gr host) |
3 | * | 3 | * |
4 | * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -366,6 +366,11 @@ int gk20a_init_ce_support(struct gk20a *g) | |||
366 | ce_app->app_state = NVGPU_CE_ACTIVE; | 366 | ce_app->app_state = NVGPU_CE_ACTIVE; |
367 | 367 | ||
368 | nvgpu_mutex_release(&ce_app->app_mutex); | 368 | nvgpu_mutex_release(&ce_app->app_mutex); |
369 | |||
370 | if (g->ops.ce2.init_prod_values != NULL) { | ||
371 | g->ops.ce2.init_prod_values(g); | ||
372 | } | ||
373 | |||
369 | nvgpu_log(g, gpu_dbg_cde_ctx, "ce: init finished"); | 374 | nvgpu_log(g, gpu_dbg_cde_ctx, "ce: init finished"); |
370 | 375 | ||
371 | return 0; | 376 | return 0; |
diff --git a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c index 2eea11df..035f2ef9 100644 --- a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Volta GPU series Copy Engine. | 2 | * Volta GPU series Copy Engine. |
3 | * | 3 | * |
4 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -108,3 +108,17 @@ void gv11b_ce_mthd_buffer_fault_in_bar2_fault(struct gk20a *g) | |||
108 | } | 108 | } |
109 | } | 109 | } |
110 | } | 110 | } |
111 | |||
112 | void gv11b_ce_init_prod_values(struct gk20a *g) | ||
113 | { | ||
114 | u32 reg_val; | ||
115 | u32 num_lce, lce; | ||
116 | |||
117 | num_lce = gv11b_ce_get_num_lce(g); | ||
118 | |||
119 | for (lce = 0U; lce < num_lce; lce++) { | ||
120 | reg_val = nvgpu_readl(g, ce_lce_opt_r(lce)); | ||
121 | reg_val |= ce_lce_opt_force_barriers_npl__prod_f(); | ||
122 | nvgpu_writel(g, ce_lce_opt_r(lce), reg_val); | ||
123 | } | ||
124 | } | ||
diff --git a/drivers/gpu/nvgpu/gv11b/ce_gv11b.h b/drivers/gpu/nvgpu/gv11b/ce_gv11b.h index 43a891e6..985117f4 100644 --- a/drivers/gpu/nvgpu/gv11b/ce_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/ce_gv11b.h | |||
@@ -2,7 +2,7 @@ | |||
2 | * | 2 | * |
3 | * Volta GPU series copy engine | 3 | * Volta GPU series copy engine |
4 | * | 4 | * |
5 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. | 5 | * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. |
6 | * | 6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | 7 | * Permission is hereby granted, free of charge, to any person obtaining a |
8 | * copy of this software and associated documentation files (the "Software"), | 8 | * copy of this software and associated documentation files (the "Software"), |
@@ -31,5 +31,6 @@ void gv11b_ce_mthd_buffer_fault_in_bar2_fault(struct gk20a *g); | |||
31 | u32 gv11b_ce_get_num_lce(struct gk20a *g); | 31 | u32 gv11b_ce_get_num_lce(struct gk20a *g); |
32 | u32 gv11b_ce_get_num_pce(struct gk20a *g); | 32 | u32 gv11b_ce_get_num_pce(struct gk20a *g); |
33 | void gv11b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base); | 33 | void gv11b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base); |
34 | void gv11b_ce_init_prod_values(struct gk20a *g); | ||
34 | 35 | ||
35 | #endif /* NVGPU_CE_GV11B_H */ | 36 | #endif /* NVGPU_CE_GV11B_H */ |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 38f21bff..4f298133 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -278,6 +278,7 @@ static const struct gpu_ops gv11b_ops = { | |||
278 | .isr_stall = gv11b_ce_isr, | 278 | .isr_stall = gv11b_ce_isr, |
279 | .isr_nonstall = gp10b_ce_nonstall_isr, | 279 | .isr_nonstall = gp10b_ce_nonstall_isr, |
280 | .get_num_pce = gv11b_ce_get_num_pce, | 280 | .get_num_pce = gv11b_ce_get_num_pce, |
281 | .init_prod_values = gv11b_ce_init_prod_values, | ||
281 | }, | 282 | }, |
282 | .gr = { | 283 | .gr = { |
283 | .get_patch_slots = gr_gv100_get_patch_slots, | 284 | .get_patch_slots = gr_gv100_get_patch_slots, |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index af8a868e..238329be 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h | |||
@@ -225,6 +225,7 @@ struct gpu_ops { | |||
225 | void (*isr_stall)(struct gk20a *g, u32 inst_id, u32 pri_base); | 225 | void (*isr_stall)(struct gk20a *g, u32 inst_id, u32 pri_base); |
226 | u32 (*isr_nonstall)(struct gk20a *g, u32 inst_id, u32 pri_base); | 226 | u32 (*isr_nonstall)(struct gk20a *g, u32 inst_id, u32 pri_base); |
227 | u32 (*get_num_pce)(struct gk20a *g); | 227 | u32 (*get_num_pce)(struct gk20a *g); |
228 | void (*init_prod_values)(struct gk20a *g); | ||
228 | } ce2; | 229 | } ce2; |
229 | struct { | 230 | struct { |
230 | u32 (*get_patch_slots)(struct gk20a *g); | 231 | u32 (*get_patch_slots)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h index efc14d00..57a76e68 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -104,4 +104,12 @@ static inline u32 ce_pce_map_r(void) | |||
104 | { | 104 | { |
105 | return 0x00104028U; | 105 | return 0x00104028U; |
106 | } | 106 | } |
107 | static inline u32 ce_lce_opt_r(u32 i) | ||
108 | { | ||
109 | return 0x00104414U + i*128U; | ||
110 | } | ||
111 | static inline u32 ce_lce_opt_force_barriers_npl__prod_f(void) | ||
112 | { | ||
113 | return 0x8U; | ||
114 | } | ||
107 | #endif | 115 | #endif |