diff options
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index c1898d2c..64716ac4 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -508,9 +508,6 @@ struct gpu_ops { | |||
508 | #endif | 508 | #endif |
509 | } fifo; | 509 | } fifo; |
510 | struct pmu_v { | 510 | struct pmu_v { |
511 | /*used for change of enum zbc update cmd id from ver 0 to ver1*/ | ||
512 | u32 cmd_id_zbc_table_update; | ||
513 | bool is_pmu_zbc_save_supported; | ||
514 | u32 (*get_pmu_cmdline_args_size)(struct nvgpu_pmu *pmu); | 511 | u32 (*get_pmu_cmdline_args_size)(struct nvgpu_pmu *pmu); |
515 | void (*set_pmu_cmdline_args_cpu_freq)(struct nvgpu_pmu *pmu, | 512 | void (*set_pmu_cmdline_args_cpu_freq)(struct nvgpu_pmu *pmu, |
516 | u32 freq); | 513 | u32 freq); |
@@ -606,6 +603,9 @@ struct gpu_ops { | |||
606 | u8 value); | 603 | u8 value); |
607 | void (*pg_cmd_eng_buf_load_set_dma_idx)(struct pmu_pg_cmd *pg, | 604 | void (*pg_cmd_eng_buf_load_set_dma_idx)(struct pmu_pg_cmd *pg, |
608 | u8 value); | 605 | u8 value); |
606 | /*used for change of enum zbc update cmd id from ver 0 to ver1*/ | ||
607 | u32 cmd_id_zbc_table_update; | ||
608 | bool is_pmu_zbc_save_supported; | ||
609 | } pmu_ver; | 609 | } pmu_ver; |
610 | struct { | 610 | struct { |
611 | int (*get_netlist_name)(struct gk20a *g, int index, char *name); | 611 | int (*get_netlist_name)(struct gk20a *g, int index, char *name); |
@@ -769,11 +769,11 @@ struct gpu_ops { | |||
769 | int (*mclk_init)(struct gk20a *g); | 769 | int (*mclk_init)(struct gk20a *g); |
770 | void (*mclk_deinit)(struct gk20a *g); | 770 | void (*mclk_deinit)(struct gk20a *g); |
771 | int (*mclk_change)(struct gk20a *g, u16 val); | 771 | int (*mclk_change)(struct gk20a *g, u16 val); |
772 | void (*handle_ext_irq)(struct gk20a *g, u32 intr); | ||
773 | void (*set_irqmask)(struct gk20a *g); | ||
772 | u32 lspmuwprinitdone; | 774 | u32 lspmuwprinitdone; |
773 | u32 lsfloadedfalconid; | 775 | u32 lsfloadedfalconid; |
774 | bool fecsbootstrapdone; | 776 | bool fecsbootstrapdone; |
775 | void (*handle_ext_irq)(struct gk20a *g, u32 intr); | ||
776 | void (*set_irqmask)(struct gk20a *g); | ||
777 | } pmu; | 777 | } pmu; |
778 | struct { | 778 | struct { |
779 | int (*init_debugfs)(struct gk20a *g); | 779 | int (*init_debugfs)(struct gk20a *g); |
@@ -811,9 +811,6 @@ struct gpu_ops { | |||
811 | struct { | 811 | struct { |
812 | int (*handle_pmu_perf_event)(struct gk20a *g, void *pmu_msg); | 812 | int (*handle_pmu_perf_event)(struct gk20a *g, void *pmu_msg); |
813 | } perf; | 813 | } perf; |
814 | bool privsecurity; | ||
815 | bool securegpccs; | ||
816 | bool pmupstate; | ||
817 | struct { | 814 | struct { |
818 | const struct regop_offset_range* ( | 815 | const struct regop_offset_range* ( |
819 | *get_global_whitelist_ranges)(void); | 816 | *get_global_whitelist_ranges)(void); |
@@ -839,7 +836,6 @@ struct gpu_ops { | |||
839 | bool enable, bool is_stalling, u32 unit); | 836 | bool enable, bool is_stalling, u32 unit); |
840 | void (*isr_stall)(struct gk20a *g); | 837 | void (*isr_stall)(struct gk20a *g); |
841 | bool (*is_intr_hub_pending)(struct gk20a *g, u32 mc_intr); | 838 | bool (*is_intr_hub_pending)(struct gk20a *g, u32 mc_intr); |
842 | u32 intr_mask_restore[4]; | ||
843 | u32 (*intr_stall)(struct gk20a *g); | 839 | u32 (*intr_stall)(struct gk20a *g); |
844 | void (*intr_stall_pause)(struct gk20a *g); | 840 | void (*intr_stall_pause)(struct gk20a *g); |
845 | void (*intr_stall_resume)(struct gk20a *g); | 841 | void (*intr_stall_resume)(struct gk20a *g); |
@@ -851,6 +847,7 @@ struct gpu_ops { | |||
851 | void (*reset)(struct gk20a *g, u32 units); | 847 | void (*reset)(struct gk20a *g, u32 units); |
852 | u32 (*boot_0)(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev); | 848 | u32 (*boot_0)(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev); |
853 | bool (*is_intr1_pending)(struct gk20a *g, enum nvgpu_unit unit, u32 mc_intr_1); | 849 | bool (*is_intr1_pending)(struct gk20a *g, enum nvgpu_unit unit, u32 mc_intr_1); |
850 | u32 intr_mask_restore[4]; | ||
854 | } mc; | 851 | } mc; |
855 | struct { | 852 | struct { |
856 | void (*show_dump)(struct gk20a *g, | 853 | void (*show_dump)(struct gk20a *g, |
@@ -938,6 +935,9 @@ struct gpu_ops { | |||
938 | struct { | 935 | struct { |
939 | void (*isr)(struct gk20a *g); | 936 | void (*isr)(struct gk20a *g); |
940 | } priv_ring; | 937 | } priv_ring; |
938 | bool privsecurity; | ||
939 | bool securegpccs; | ||
940 | bool pmupstate; | ||
941 | }; | 941 | }; |
942 | 942 | ||
943 | struct nvgpu_bios_ucode { | 943 | struct nvgpu_bios_ucode { |