diff options
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index c7c2e8af..71e21d58 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c | |||
@@ -46,6 +46,26 @@ static struct pll_parms gpc_pll_params = { | |||
46 | static int clk_gm20b_debugfs_init(struct gk20a *g); | 46 | static int clk_gm20b_debugfs_init(struct gk20a *g); |
47 | #endif | 47 | #endif |
48 | 48 | ||
49 | #define DUMP_REG(addr_func) \ | ||
50 | do { \ | ||
51 | addr = trim_sys_##addr_func##_r(); \ | ||
52 | data = gk20a_readl(g, addr); \ | ||
53 | pr_info(#addr_func "[0x%x] = 0x%x\n", addr, data); \ | ||
54 | } while (0) | ||
55 | |||
56 | static void dump_gpc_pll(struct gk20a *g, struct pll *gpll, u32 last_cfg) | ||
57 | { | ||
58 | u32 addr, data; | ||
59 | |||
60 | pr_info("**** GPCPLL DUMP ****"); | ||
61 | pr_info("gpcpll s/w M=%u N=%u P=%u\n", gpll->M, gpll->N, gpll->PL); | ||
62 | pr_info("gpcpll_cfg_last = 0x%x\n", last_cfg); | ||
63 | DUMP_REG(gpcpll_cfg); | ||
64 | DUMP_REG(gpcpll_coeff); | ||
65 | DUMP_REG(sel_vco); | ||
66 | pr_info("\n"); | ||
67 | } | ||
68 | |||
49 | /* 1:1 match between post divider settings and divisor value */ | 69 | /* 1:1 match between post divider settings and divisor value */ |
50 | static inline u32 pl_to_div(u32 pl) | 70 | static inline u32 pl_to_div(u32 pl) |
51 | { | 71 | { |
@@ -344,6 +364,7 @@ static int clk_lock_gpc_pll_under_bypass(struct gk20a *g, struct pll *gpll) | |||
344 | } while (--timeout > 0); | 364 | } while (--timeout > 0); |
345 | 365 | ||
346 | /* PLL is messed up. What can we do here? */ | 366 | /* PLL is messed up. What can we do here? */ |
367 | dump_gpc_pll(g, gpll, cfg); | ||
347 | BUG(); | 368 | BUG(); |
348 | return -EBUSY; | 369 | return -EBUSY; |
349 | 370 | ||