diff options
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 81 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | 33 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/fifo_gm20b.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/fifo_gp106.c | 71 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/fifo_gp106.h | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/fifo_gp10b.c | 56 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/fifo_gp10b.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 3 |
16 files changed, 244 insertions, 39 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index fc63dcbe..75d66968 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -1143,7 +1143,7 @@ gk20a_refch_from_inst_ptr(struct gk20a *g, u64 inst_ptr) | |||
1143 | /* fault info/descriptions. | 1143 | /* fault info/descriptions. |
1144 | * tbd: move to setup | 1144 | * tbd: move to setup |
1145 | * */ | 1145 | * */ |
1146 | static const char * const fault_type_descs[] = { | 1146 | static const char * const gk20a_fault_type_descs[] = { |
1147 | "pde", /*fifo_intr_mmu_fault_info_type_pde_v() == 0 */ | 1147 | "pde", /*fifo_intr_mmu_fault_info_type_pde_v() == 0 */ |
1148 | "pde size", | 1148 | "pde size", |
1149 | "pte", | 1149 | "pte", |
@@ -1167,15 +1167,15 @@ static const char * const engine_subid_descs[] = { | |||
1167 | "hub", | 1167 | "hub", |
1168 | }; | 1168 | }; |
1169 | 1169 | ||
1170 | static const char * const hub_client_descs[] = { | 1170 | static const char * const gk20a_hub_client_descs[] = { |
1171 | "vip", "ce0", "ce1", "dniso", "fe", "fecs", "host", "host cpu", | 1171 | "vip", "ce0", "ce1", "dniso", "fe", "fecs", "host", "host cpu", |
1172 | "host cpu nb", "iso", "mmu", "mspdec", "msppp", "msvld", | 1172 | "host cpu nb", "iso", "mmu", "mspdec", "msppp", "msvld", |
1173 | "niso", "p2p", "pd", "perf", "pmu", "raster twod", "scc", | 1173 | "niso", "p2p", "pd", "perf", "pmu", "raster twod", "scc", |
1174 | "scc nb", "sec", "ssync", "gr copy", "ce2", "xv", "mmu nb", | 1174 | "scc nb", "sec", "ssync", "gr copy", "xv", "mmu nb", |
1175 | "msenc", "d falcon", "sked", "a falcon", "n/a", | 1175 | "msenc", "d falcon", "sked", "a falcon", "n/a", |
1176 | }; | 1176 | }; |
1177 | 1177 | ||
1178 | static const char * const gpc_client_descs[] = { | 1178 | static const char * const gk20a_gpc_client_descs[] = { |
1179 | "l1 0", "t1 0", "pe 0", | 1179 | "l1 0", "t1 0", "pe 0", |
1180 | "l1 1", "t1 1", "pe 1", | 1180 | "l1 1", "t1 1", "pe 1", |
1181 | "l1 2", "t1 2", "pe 2", | 1181 | "l1 2", "t1 2", "pe 2", |
@@ -1186,28 +1186,54 @@ static const char * const gpc_client_descs[] = { | |||
1186 | "l1 5", "t1 5", "pe 5", | 1186 | "l1 5", "t1 5", "pe 5", |
1187 | "l1 6", "t1 6", "pe 6", | 1187 | "l1 6", "t1 6", "pe 6", |
1188 | "l1 7", "t1 7", "pe 7", | 1188 | "l1 7", "t1 7", "pe 7", |
1189 | "gpm", | ||
1190 | "ltp utlb 0", "ltp utlb 1", "ltp utlb 2", "ltp utlb 3", | ||
1191 | "rgg utlb", | ||
1192 | }; | 1189 | }; |
1193 | 1190 | ||
1194 | static const char * const does_not_exist[] = { | 1191 | static const char * const does_not_exist[] = { |
1195 | "does not exist" | 1192 | "does not exist" |
1196 | }; | 1193 | }; |
1197 | 1194 | ||
1195 | /* fill in mmu fault desc */ | ||
1196 | void gk20a_fifo_get_mmu_fault_desc(struct mmu_fault_info *mmfault) | ||
1197 | { | ||
1198 | if (mmfault->fault_type >= ARRAY_SIZE(gk20a_fault_type_descs)) | ||
1199 | WARN_ON(mmfault->fault_type >= | ||
1200 | ARRAY_SIZE(gk20a_fault_type_descs)); | ||
1201 | else | ||
1202 | mmfault->fault_type_desc = | ||
1203 | gk20a_fault_type_descs[mmfault->fault_type]; | ||
1204 | } | ||
1205 | |||
1206 | /* fill in mmu fault client description */ | ||
1207 | void gk20a_fifo_get_mmu_fault_client_desc(struct mmu_fault_info *mmfault) | ||
1208 | { | ||
1209 | if (mmfault->client_id >= ARRAY_SIZE(gk20a_hub_client_descs)) | ||
1210 | WARN_ON(mmfault->client_id >= | ||
1211 | ARRAY_SIZE(gk20a_hub_client_descs)); | ||
1212 | else | ||
1213 | mmfault->client_id_desc = | ||
1214 | gk20a_hub_client_descs[mmfault->client_id]; | ||
1215 | } | ||
1216 | |||
1217 | /* fill in mmu fault gpc description */ | ||
1218 | void gk20a_fifo_get_mmu_fault_gpc_desc(struct mmu_fault_info *mmfault) | ||
1219 | { | ||
1220 | if (mmfault->client_id >= ARRAY_SIZE(gk20a_gpc_client_descs)) | ||
1221 | WARN_ON(mmfault->client_id >= | ||
1222 | ARRAY_SIZE(gk20a_gpc_client_descs)); | ||
1223 | else | ||
1224 | mmfault->client_id_desc = | ||
1225 | gk20a_gpc_client_descs[mmfault->client_id]; | ||
1226 | } | ||
1227 | |||
1198 | static void get_exception_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id, | 1228 | static void get_exception_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id, |
1199 | struct mmu_fault_info *mmfault) | 1229 | struct mmu_fault_info *mmfault) |
1200 | { | 1230 | { |
1201 | g->ops.fifo.get_mmu_fault_info(g, mmu_fault_id, mmfault); | 1231 | g->ops.fifo.get_mmu_fault_info(g, mmu_fault_id, mmfault); |
1202 | 1232 | ||
1203 | /* parse info */ | 1233 | /* parse info */ |
1204 | if (mmfault->fault_type >= ARRAY_SIZE(fault_type_descs)) { | 1234 | mmfault->fault_type_desc = does_not_exist[0]; |
1205 | WARN_ON(mmfault->fault_type >= ARRAY_SIZE(fault_type_descs)); | 1235 | if (g->ops.fifo.get_mmu_fault_desc) |
1206 | mmfault->fault_type_desc = does_not_exist[0]; | 1236 | g->ops.fifo.get_mmu_fault_desc(mmfault); |
1207 | } else { | ||
1208 | mmfault->fault_type_desc = | ||
1209 | fault_type_descs[mmfault->fault_type]; | ||
1210 | } | ||
1211 | 1237 | ||
1212 | if (mmfault->client_type >= ARRAY_SIZE(engine_subid_descs)) { | 1238 | if (mmfault->client_type >= ARRAY_SIZE(engine_subid_descs)) { |
1213 | WARN_ON(mmfault->client_type >= ARRAY_SIZE(engine_subid_descs)); | 1239 | WARN_ON(mmfault->client_type >= ARRAY_SIZE(engine_subid_descs)); |
@@ -1218,25 +1244,14 @@ static void get_exception_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id, | |||
1218 | } | 1244 | } |
1219 | 1245 | ||
1220 | mmfault->client_id_desc = does_not_exist[0]; | 1246 | mmfault->client_id_desc = does_not_exist[0]; |
1221 | if (mmfault->client_type == | 1247 | if ((mmfault->client_type == |
1222 | fifo_intr_mmu_fault_info_engine_subid_hub_v()) { | 1248 | fifo_intr_mmu_fault_info_engine_subid_hub_v()) |
1223 | 1249 | && g->ops.fifo.get_mmu_fault_client_desc) | |
1224 | if (mmfault->client_id >= | 1250 | g->ops.fifo.get_mmu_fault_client_desc(mmfault); |
1225 | ARRAY_SIZE(hub_client_descs)) | 1251 | else if ((mmfault->client_type == |
1226 | WARN_ON(mmfault->client_id >= | 1252 | fifo_intr_mmu_fault_info_engine_subid_gpc_v()) |
1227 | ARRAY_SIZE(hub_client_descs)); | 1253 | && g->ops.fifo.get_mmu_fault_gpc_desc) |
1228 | else | 1254 | g->ops.fifo.get_mmu_fault_gpc_desc(mmfault); |
1229 | mmfault->client_id_desc = | ||
1230 | hub_client_descs[mmfault->client_id]; | ||
1231 | } else if (mmfault->client_type == | ||
1232 | fifo_intr_mmu_fault_info_engine_subid_gpc_v()) { | ||
1233 | if (mmfault->client_id >= ARRAY_SIZE(gpc_client_descs)) | ||
1234 | WARN_ON(mmfault->client_id >= | ||
1235 | ARRAY_SIZE(gpc_client_descs)); | ||
1236 | else | ||
1237 | mmfault->client_id_desc = | ||
1238 | gpc_client_descs[mmfault->client_id]; | ||
1239 | } | ||
1240 | } | 1255 | } |
1241 | 1256 | ||
1242 | /* reads info from hardware and fills in mmu fault info record */ | 1257 | /* reads info from hardware and fills in mmu fault info record */ |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index c4f7f8ac..20533f5d 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | |||
@@ -441,4 +441,7 @@ int gk20a_fifo_alloc_syncpt_buf(struct channel_gk20a *c, | |||
441 | 441 | ||
442 | void gk20a_fifo_get_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id, | 442 | void gk20a_fifo_get_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id, |
443 | struct mmu_fault_info *mmfault); | 443 | struct mmu_fault_info *mmfault); |
444 | void gk20a_fifo_get_mmu_fault_desc(struct mmu_fault_info *mmfault); | ||
445 | void gk20a_fifo_get_mmu_fault_client_desc(struct mmu_fault_info *mmfault); | ||
446 | void gk20a_fifo_get_mmu_fault_gpc_desc(struct mmu_fault_info *mmfault); | ||
444 | #endif /*__GR_GK20A_H__*/ | 447 | #endif /*__GR_GK20A_H__*/ |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index e48af08c..2d47f41e 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -574,6 +574,10 @@ struct gpu_ops { | |||
574 | unsigned long engine_ids); | 574 | unsigned long engine_ids); |
575 | void (*get_mmu_fault_info)(struct gk20a *g, u32 mmu_fault_id, | 575 | void (*get_mmu_fault_info)(struct gk20a *g, u32 mmu_fault_id, |
576 | struct mmu_fault_info *mmfault); | 576 | struct mmu_fault_info *mmfault); |
577 | void (*get_mmu_fault_desc)(struct mmu_fault_info *mmfault); | ||
578 | void (*get_mmu_fault_client_desc)( | ||
579 | struct mmu_fault_info *mmfault); | ||
580 | void (*get_mmu_fault_gpc_desc)(struct mmu_fault_info *mmfault); | ||
577 | void (*apply_pb_timeout)(struct gk20a *g); | 581 | void (*apply_pb_timeout)(struct gk20a *g); |
578 | void (*apply_ctxsw_timeout_intr)(struct gk20a *g); | 582 | void (*apply_ctxsw_timeout_intr)(struct gk20a *g); |
579 | int (*wait_engine_idle)(struct gk20a *g); | 583 | int (*wait_engine_idle)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c index 15612995..35a7a9e1 100644 --- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B Fifo | 2 | * GM20B Fifo |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -223,3 +223,34 @@ void gm20b_fifo_tsg_verify_status_ctx_reload(struct channel_gk20a *ch) | |||
223 | nvgpu_rwsem_up_read(&tsg->ch_list_lock); | 223 | nvgpu_rwsem_up_read(&tsg->ch_list_lock); |
224 | } | 224 | } |
225 | } | 225 | } |
226 | |||
227 | static const char * const gm20b_gpc_client_descs[] = { | ||
228 | "l1 0", "t1 0", "pe 0", | ||
229 | "l1 1", "t1 1", "pe 1", | ||
230 | "l1 2", "t1 2", "pe 2", | ||
231 | "l1 3", "t1 3", "pe 3", | ||
232 | "rast", "gcc", "gpccs", | ||
233 | "prop 0", "prop 1", "prop 2", "prop 3", | ||
234 | "l1 4", "t1 4", "pe 4", | ||
235 | "l1 5", "t1 5", "pe 5", | ||
236 | "l1 6", "t1 6", "pe 6", | ||
237 | "l1 7", "t1 7", "pe 7", | ||
238 | "l1 9", "t1 9", "pe 9", | ||
239 | "l1 10", "t1 10", "pe 10", | ||
240 | "l1 11", "t1 11", "pe 11", | ||
241 | "unknown", "unknown", "unknown", "unknown", | ||
242 | "tpccs 0", "tpccs 1", "tpccs 2", | ||
243 | "tpccs 3", "tpccs 4", "tpccs 5", | ||
244 | "tpccs 6", "tpccs 7", "tpccs 8", | ||
245 | "tpccs 9", "tpccs 10", "tpccs 11", | ||
246 | }; | ||
247 | |||
248 | void gm20b_fifo_get_mmu_fault_gpc_desc(struct mmu_fault_info *mmfault) | ||
249 | { | ||
250 | if (mmfault->client_id >= ARRAY_SIZE(gm20b_gpc_client_descs)) | ||
251 | WARN_ON(mmfault->client_id >= | ||
252 | ARRAY_SIZE(gm20b_gpc_client_descs)); | ||
253 | else | ||
254 | mmfault->client_id_desc = | ||
255 | gm20b_gpc_client_descs[mmfault->client_id]; | ||
256 | } | ||
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h index 8d487358..f9e1f95d 100644 --- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B Fifo | 2 | * GM20B Fifo |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -25,6 +25,7 @@ | |||
25 | #ifndef _NVHOST_GM20B_FIFO | 25 | #ifndef _NVHOST_GM20B_FIFO |
26 | #define _NVHOST_GM20B_FIFO | 26 | #define _NVHOST_GM20B_FIFO |
27 | struct gk20a; | 27 | struct gk20a; |
28 | struct mmu_fault_info; | ||
28 | 29 | ||
29 | void channel_gm20b_bind(struct channel_gk20a *c); | 30 | void channel_gm20b_bind(struct channel_gk20a *c); |
30 | void gm20b_fifo_trigger_mmu_fault(struct gk20a *g, | 31 | void gm20b_fifo_trigger_mmu_fault(struct gk20a *g, |
@@ -35,5 +36,6 @@ void gm20b_device_info_data_parse(struct gk20a *g, | |||
35 | u32 *pri_base, u32 *fault_id); | 36 | u32 *pri_base, u32 *fault_id); |
36 | void gm20b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f); | 37 | void gm20b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f); |
37 | void gm20b_fifo_tsg_verify_status_ctx_reload(struct channel_gk20a *ch); | 38 | void gm20b_fifo_tsg_verify_status_ctx_reload(struct channel_gk20a *ch); |
39 | void gm20b_fifo_get_mmu_fault_gpc_desc(struct mmu_fault_info *mmfault); | ||
38 | 40 | ||
39 | #endif | 41 | #endif |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 76837ab7..328c1c38 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -416,6 +416,9 @@ static const struct gpu_ops gm20b_ops = { | |||
416 | .update_runlist = gk20a_fifo_update_runlist, | 416 | .update_runlist = gk20a_fifo_update_runlist, |
417 | .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault, | 417 | .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault, |
418 | .get_mmu_fault_info = gk20a_fifo_get_mmu_fault_info, | 418 | .get_mmu_fault_info = gk20a_fifo_get_mmu_fault_info, |
419 | .get_mmu_fault_desc = gk20a_fifo_get_mmu_fault_desc, | ||
420 | .get_mmu_fault_client_desc = gk20a_fifo_get_mmu_fault_client_desc, | ||
421 | .get_mmu_fault_gpc_desc = gm20b_fifo_get_mmu_fault_gpc_desc, | ||
419 | .wait_engine_idle = gk20a_fifo_wait_engine_idle, | 422 | .wait_engine_idle = gk20a_fifo_wait_engine_idle, |
420 | .get_num_fifos = gm20b_fifo_get_num_fifos, | 423 | .get_num_fifos = gm20b_fifo_get_num_fifos, |
421 | .get_pbdma_signature = gk20a_fifo_get_pbdma_signature, | 424 | .get_pbdma_signature = gk20a_fifo_get_pbdma_signature, |
diff --git a/drivers/gpu/nvgpu/gp106/fifo_gp106.c b/drivers/gpu/nvgpu/gp106/fifo_gp106.c index 77c09262..9b1dd768 100644 --- a/drivers/gpu/nvgpu/gp106/fifo_gp106.c +++ b/drivers/gpu/nvgpu/gp106/fifo_gp106.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -32,3 +32,72 @@ u32 gp106_fifo_get_num_fifos(struct gk20a *g) | |||
32 | { | 32 | { |
33 | return ccsr_channel__size_1_v(); | 33 | return ccsr_channel__size_1_v(); |
34 | } | 34 | } |
35 | |||
36 | static const char * const gp106_hub_client_descs[] = { | ||
37 | "vip", "ce0", "ce1", "dniso", "fe", "fecs", "host", "host cpu", | ||
38 | "host cpu nb", "iso", "mmu", "mspdec", "msppp", "msvld", | ||
39 | "niso", "p2p", "pd", "perf", "pmu", "raster twod", "scc", | ||
40 | "scc nb", "sec", "ssync", "gr copy", "xv", "mmu nb", | ||
41 | "msenc", "d falcon", "sked", "a falcon", "n/a", | ||
42 | "hsce0", "hsce1", "hsce2", "hsce3", "hsce4", "hsce5", | ||
43 | "hsce6", "hsce7", "hsce8", "hsce9", "hshub", | ||
44 | "ptp x0", "ptp x1", "ptp x2", "ptp x3", "ptp x4", | ||
45 | "ptp x5", "ptp x6", "ptp x7", "vpr scrubber0", "vpr scrubber1", | ||
46 | "dwbif", "fbfalcon", | ||
47 | }; | ||
48 | |||
49 | static const char * const gp106_gpc_client_descs[] = { | ||
50 | "l1 0", "t1 0", "pe 0", | ||
51 | "l1 1", "t1 1", "pe 1", | ||
52 | "l1 2", "t1 2", "pe 2", | ||
53 | "l1 3", "t1 3", "pe 3", | ||
54 | "rast", "gcc", "gpccs", | ||
55 | "prop 0", "prop 1", "prop 2", "prop 3", | ||
56 | "l1 4", "t1 4", "pe 4", | ||
57 | "l1 5", "t1 5", "pe 5", | ||
58 | "l1 6", "t1 6", "pe 6", | ||
59 | "l1 7", "t1 7", "pe 7", | ||
60 | "l1 9", "t1 9", "pe 9", | ||
61 | "l1 10", "t1 10", "pe 10", | ||
62 | "l1 11", "t1 11", "pe 11", | ||
63 | "unknown", "unknown", "unknown", "unknown", | ||
64 | "tpccs 0", "tpccs 1", "tpccs 2", | ||
65 | "tpccs 3", "tpccs 4", "tpccs 5", | ||
66 | "tpccs 6", "tpccs 7", "tpccs 8", | ||
67 | "tpccs 9", "tpccs 10", "tpccs 11", | ||
68 | "tpccs 12", "tpccs 13", "tpccs 14", | ||
69 | "tpccs 15", "tpccs 16", "tpccs 17", | ||
70 | "tpccs 18", "tpccs 19", "unknown", "unknown", | ||
71 | "unknown", "unknown", "unknown", "unknown", | ||
72 | "unknown", "unknown", "unknown", "unknown", | ||
73 | "unknown", "unknown", | ||
74 | "l1 12", "t1 12", "pe 12", | ||
75 | "l1 13", "t1 13", "pe 13", | ||
76 | "l1 14", "t1 14", "pe 14", | ||
77 | "l1 15", "t1 15", "pe 15", | ||
78 | "l1 16", "t1 16", "pe 16", | ||
79 | "l1 17", "t1 17", "pe 17", | ||
80 | "l1 18", "t1 18", "pe 18", | ||
81 | "l1 19", "t1 19", "pe 19", | ||
82 | }; | ||
83 | |||
84 | void gp106_fifo_get_mmu_fault_gpc_desc(struct mmu_fault_info *mmfault) | ||
85 | { | ||
86 | if (mmfault->client_id >= ARRAY_SIZE(gp106_gpc_client_descs)) | ||
87 | WARN_ON(mmfault->client_id >= | ||
88 | ARRAY_SIZE(gp106_gpc_client_descs)); | ||
89 | else | ||
90 | mmfault->client_id_desc = | ||
91 | gp106_gpc_client_descs[mmfault->client_id]; | ||
92 | } | ||
93 | |||
94 | /* fill in mmu fault client description */ | ||
95 | void gp106_fifo_get_mmu_fault_client_desc(struct mmu_fault_info *mmfault) | ||
96 | { | ||
97 | if (mmfault->client_id >= ARRAY_SIZE(gp106_hub_client_descs)) | ||
98 | WARN_ON(mmfault->client_id >= | ||
99 | ARRAY_SIZE(gp106_hub_client_descs)); | ||
100 | else | ||
101 | mmfault->client_id_desc = | ||
102 | gp106_hub_client_descs[mmfault->client_id]; | ||
103 | } | ||
diff --git a/drivers/gpu/nvgpu/gp106/fifo_gp106.h b/drivers/gpu/nvgpu/gp106/fifo_gp106.h index 37b3f3e7..a6436a1b 100644 --- a/drivers/gpu/nvgpu/gp106/fifo_gp106.h +++ b/drivers/gpu/nvgpu/gp106/fifo_gp106.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -23,5 +23,9 @@ | |||
23 | #ifndef NVGPU_FIFO_GP106_H | 23 | #ifndef NVGPU_FIFO_GP106_H |
24 | #define NVGPU_FIFO_GP106_H | 24 | #define NVGPU_FIFO_GP106_H |
25 | struct gk20a; | 25 | struct gk20a; |
26 | struct mmu_fault_info; | ||
27 | |||
26 | u32 gp106_fifo_get_num_fifos(struct gk20a *g); | 28 | u32 gp106_fifo_get_num_fifos(struct gk20a *g); |
29 | void gp106_fifo_get_mmu_fault_client_desc(struct mmu_fault_info *mmfault); | ||
30 | void gp106_fifo_get_mmu_fault_gpc_desc(struct mmu_fault_info *mmfault); | ||
27 | #endif | 31 | #endif |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 43b1d2e0..03e3bd07 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -478,6 +478,9 @@ static const struct gpu_ops gp106_ops = { | |||
478 | .update_runlist = gk20a_fifo_update_runlist, | 478 | .update_runlist = gk20a_fifo_update_runlist, |
479 | .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault, | 479 | .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault, |
480 | .get_mmu_fault_info = gp10b_fifo_get_mmu_fault_info, | 480 | .get_mmu_fault_info = gp10b_fifo_get_mmu_fault_info, |
481 | .get_mmu_fault_desc = gp10b_fifo_get_mmu_fault_desc, | ||
482 | .get_mmu_fault_client_desc = gp106_fifo_get_mmu_fault_client_desc, | ||
483 | .get_mmu_fault_gpc_desc = gp106_fifo_get_mmu_fault_gpc_desc, | ||
481 | .wait_engine_idle = gk20a_fifo_wait_engine_idle, | 484 | .wait_engine_idle = gk20a_fifo_wait_engine_idle, |
482 | .get_num_fifos = gp106_fifo_get_num_fifos, | 485 | .get_num_fifos = gp106_fifo_get_num_fifos, |
483 | .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, | 486 | .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, |
diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c index 1436a260..66f3012f 100644 --- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GP10B fifo | 2 | * GP10B fifo |
3 | * | 3 | * |
4 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -317,3 +317,57 @@ void gp10b_fifo_get_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id, | |||
317 | /* note: inst_ptr is a 40b phys addr. */ | 317 | /* note: inst_ptr is a 40b phys addr. */ |
318 | mmfault->inst_ptr <<= fifo_intr_mmu_fault_inst_ptr_align_shift_v(); | 318 | mmfault->inst_ptr <<= fifo_intr_mmu_fault_inst_ptr_align_shift_v(); |
319 | } | 319 | } |
320 | /* fault info/descriptions */ | ||
321 | static const char * const gp10b_fault_type_descs[] = { | ||
322 | "pde", /*fifo_intr_mmu_fault_info_type_pde_v() == 0 */ | ||
323 | "pde size", | ||
324 | "pte", | ||
325 | "va limit viol", | ||
326 | "unbound inst", | ||
327 | "priv viol", | ||
328 | "ro viol", | ||
329 | "wo viol", | ||
330 | "pitch mask", | ||
331 | "work creation", | ||
332 | "bad aperture", | ||
333 | "compression failure", | ||
334 | "bad kind", | ||
335 | "region viol", | ||
336 | "dual ptes", | ||
337 | "poisoned", | ||
338 | "atomic violation", | ||
339 | }; | ||
340 | |||
341 | static const char * const gp10b_hub_client_descs[] = { | ||
342 | "vip", "ce0", "ce1", "dniso", "fe", "fecs", "host", "host cpu", | ||
343 | "host cpu nb", "iso", "mmu", "mspdec", "msppp", "msvld", | ||
344 | "niso", "p2p", "pd", "perf", "pmu", "raster twod", "scc", | ||
345 | "scc nb", "sec", "ssync", "gr copy", "xv", "mmu nb", | ||
346 | "msenc", "d falcon", "sked", "a falcon", "n/a", | ||
347 | "hsce0", "hsce1", "hsce2", "hsce3", "hsce4", "hsce5", | ||
348 | "hsce6", "hsce7", "hsce8", "hsce9", "hshub", | ||
349 | "ptp x0", "ptp x1", "ptp x2", "ptp x3", "ptp x4", | ||
350 | "ptp x5", "ptp x6", "ptp x7", "vpr scrubber0", "vpr scrubber1", | ||
351 | }; | ||
352 | |||
353 | /* fill in mmu fault desc */ | ||
354 | void gp10b_fifo_get_mmu_fault_desc(struct mmu_fault_info *mmfault) | ||
355 | { | ||
356 | if (mmfault->fault_type >= ARRAY_SIZE(gp10b_fault_type_descs)) | ||
357 | WARN_ON(mmfault->fault_type >= | ||
358 | ARRAY_SIZE(gp10b_fault_type_descs)); | ||
359 | else | ||
360 | mmfault->fault_type_desc = | ||
361 | gp10b_fault_type_descs[mmfault->fault_type]; | ||
362 | } | ||
363 | |||
364 | /* fill in mmu fault client description */ | ||
365 | void gp10b_fifo_get_mmu_fault_client_desc(struct mmu_fault_info *mmfault) | ||
366 | { | ||
367 | if (mmfault->client_id >= ARRAY_SIZE(gp10b_hub_client_descs)) | ||
368 | WARN_ON(mmfault->client_id >= | ||
369 | ARRAY_SIZE(gp10b_hub_client_descs)); | ||
370 | else | ||
371 | mmfault->client_id_desc = | ||
372 | gp10b_hub_client_descs[mmfault->client_id]; | ||
373 | } | ||
diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.h b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.h index 20918483..2ab11eca 100644 --- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GP10B Fifo | 2 | * GP10B Fifo |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -42,6 +42,8 @@ void gp10b_device_info_data_parse(struct gk20a *g, u32 table_entry, | |||
42 | void gp10b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f); | 42 | void gp10b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f); |
43 | void gp10b_fifo_get_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id, | 43 | void gp10b_fifo_get_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id, |
44 | struct mmu_fault_info *mmfault); | 44 | struct mmu_fault_info *mmfault); |
45 | void gp10b_fifo_get_mmu_fault_desc(struct mmu_fault_info *mmfault); | ||
46 | void gp10b_fifo_get_mmu_fault_client_desc(struct mmu_fault_info *mmfault); | ||
45 | int channel_gp10b_commit_userd(struct channel_gk20a *c); | 47 | int channel_gp10b_commit_userd(struct channel_gk20a *c); |
46 | 48 | ||
47 | #endif | 49 | #endif |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 42350dbc..f0c6b410 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -451,6 +451,9 @@ static const struct gpu_ops gp10b_ops = { | |||
451 | .update_runlist = gk20a_fifo_update_runlist, | 451 | .update_runlist = gk20a_fifo_update_runlist, |
452 | .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault, | 452 | .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault, |
453 | .get_mmu_fault_info = gp10b_fifo_get_mmu_fault_info, | 453 | .get_mmu_fault_info = gp10b_fifo_get_mmu_fault_info, |
454 | .get_mmu_fault_desc = gp10b_fifo_get_mmu_fault_desc, | ||
455 | .get_mmu_fault_client_desc = gp10b_fifo_get_mmu_fault_client_desc, | ||
456 | .get_mmu_fault_gpc_desc = gm20b_fifo_get_mmu_fault_gpc_desc, | ||
454 | .wait_engine_idle = gk20a_fifo_wait_engine_idle, | 457 | .wait_engine_idle = gk20a_fifo_wait_engine_idle, |
455 | .get_num_fifos = gm20b_fifo_get_num_fifos, | 458 | .get_num_fifos = gm20b_fifo_get_num_fifos, |
456 | .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, | 459 | .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 517c1ac6..838dbf87 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -534,6 +534,9 @@ static const struct gpu_ops gv100_ops = { | |||
534 | .update_runlist = gk20a_fifo_update_runlist, | 534 | .update_runlist = gk20a_fifo_update_runlist, |
535 | .trigger_mmu_fault = NULL, | 535 | .trigger_mmu_fault = NULL, |
536 | .get_mmu_fault_info = NULL, | 536 | .get_mmu_fault_info = NULL, |
537 | .get_mmu_fault_desc = NULL, | ||
538 | .get_mmu_fault_client_desc = NULL, | ||
539 | .get_mmu_fault_gpc_desc = NULL, | ||
537 | .wait_engine_idle = gk20a_fifo_wait_engine_idle, | 540 | .wait_engine_idle = gk20a_fifo_wait_engine_idle, |
538 | .get_num_fifos = gv100_fifo_get_num_fifos, | 541 | .get_num_fifos = gv100_fifo_get_num_fifos, |
539 | .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, | 542 | .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index a2ee3206..76820d2e 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -506,6 +506,9 @@ static const struct gpu_ops gv11b_ops = { | |||
506 | .update_runlist = gk20a_fifo_update_runlist, | 506 | .update_runlist = gk20a_fifo_update_runlist, |
507 | .trigger_mmu_fault = NULL, | 507 | .trigger_mmu_fault = NULL, |
508 | .get_mmu_fault_info = NULL, | 508 | .get_mmu_fault_info = NULL, |
509 | .get_mmu_fault_desc = NULL, | ||
510 | .get_mmu_fault_client_desc = NULL, | ||
511 | .get_mmu_fault_gpc_desc = NULL, | ||
509 | .wait_engine_idle = gk20a_fifo_wait_engine_idle, | 512 | .wait_engine_idle = gk20a_fifo_wait_engine_idle, |
510 | .get_num_fifos = gv11b_fifo_get_num_fifos, | 513 | .get_num_fifos = gv11b_fifo_get_num_fifos, |
511 | .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, | 514 | .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, |
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index 73543baf..78b8d012 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | |||
@@ -323,6 +323,9 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
323 | .update_runlist = vgpu_fifo_update_runlist, | 323 | .update_runlist = vgpu_fifo_update_runlist, |
324 | .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault, | 324 | .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault, |
325 | .get_mmu_fault_info = gp10b_fifo_get_mmu_fault_info, | 325 | .get_mmu_fault_info = gp10b_fifo_get_mmu_fault_info, |
326 | .get_mmu_fault_desc = gp10b_fifo_get_mmu_fault_desc, | ||
327 | .get_mmu_fault_client_desc = gp10b_fifo_get_mmu_fault_client_desc, | ||
328 | .get_mmu_fault_gpc_desc = gm20b_fifo_get_mmu_fault_gpc_desc, | ||
326 | .wait_engine_idle = vgpu_fifo_wait_engine_idle, | 329 | .wait_engine_idle = vgpu_fifo_wait_engine_idle, |
327 | .get_num_fifos = gm20b_fifo_get_num_fifos, | 330 | .get_num_fifos = gm20b_fifo_get_num_fifos, |
328 | .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, | 331 | .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, |
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 8128054e..deb5f37f 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | |||
@@ -362,6 +362,9 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
362 | .update_runlist = vgpu_fifo_update_runlist, | 362 | .update_runlist = vgpu_fifo_update_runlist, |
363 | .trigger_mmu_fault = NULL, | 363 | .trigger_mmu_fault = NULL, |
364 | .get_mmu_fault_info = NULL, | 364 | .get_mmu_fault_info = NULL, |
365 | .get_mmu_fault_desc = NULL, | ||
366 | .get_mmu_fault_client_desc = NULL, | ||
367 | .get_mmu_fault_gpc_desc = NULL, | ||
365 | .wait_engine_idle = vgpu_fifo_wait_engine_idle, | 368 | .wait_engine_idle = vgpu_fifo_wait_engine_idle, |
366 | .get_num_fifos = gv11b_fifo_get_num_fifos, | 369 | .get_num_fifos = gv11b_fifo_get_num_fifos, |
367 | .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, | 370 | .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, |