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| author | Anup Mahindre <amahindre@nvidia.com> | 2018-09-21 02:22:47 -0400 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-09-27 18:06:37 -0400 |
| commit | 30b571e31c7f8ee26fc58864272bc7c7e083d377 (patch) | |
| tree | 9c45ffa9c6df41880163884ebdbab57a9920d041 /userspace/units/posix-env/posix-env.export | |
| parent | f89ea110417e1c83cf21f495d6da7cdc8138a29f (diff) | |
gpu: nvgpu: Add gv11b_gr_clear_sm_error_state
All chips were currently using gm20b_gr_clear_sm_error_state
It was wrong for chips based on volta and later as the implementation didn't
consider non pes-aware vsms mapping
Add new HAL implementation for clear_sm_error_state for volta based and later
chips to fix this.
Bug 200448172
Change-Id: I65988c8cbb35d13089ac628e8333d9a3b58e0eb1
Signed-off-by: Anup Mahindre <amahindre@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1837188
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'userspace/units/posix-env/posix-env.export')
0 files changed, 0 insertions, 0 deletions