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| author | Vinod G <vinodg@nvidia.com> | 2018-08-29 15:32:25 -0400 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-08-31 21:57:23 -0400 |
| commit | f187e0bf442c3b0a08c46b21196f06a18c8220a0 (patch) | |
| tree | 48820c076f6ab4a2bad6ab6053d26293c99326c3 /scripts | |
| parent | b25d5d86caa049201ddcea77cf1a733a85090698 (diff) | |
gpu: nvgpu: Move SM_MASK_TYPE setting to TSG level
Moved the SM_MASK_TYPE variable from GR to
TSG struct. SM error registers are context based.
In dbg_session IOCTL to SET_SM_MASK_TYPE, kernel
code iterate the TSG associated with first channel
and set the mask_type to that context.
Bug 200412641
Change-Id: Ic91944037ad2447f403b4803d5266ae6250ba4c9
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809322
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions