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| author | Seema Khowala <seemaj@nvidia.com> | 2017-01-13 17:24:36 -0500 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-01-18 19:46:10 -0500 |
| commit | a674eeee419a68e27bec63e46200036f5f33c8ff (patch) | |
| tree | b1af36cb70b39f66cbe0ff0f399fa54806f7109b /scripts | |
| parent | 4ad2d3aebc4137d350efaff8072d60441572bcf2 (diff) | |
gpu: nvgpu: gv11b: Support Stencil ZBC
Pre-GP10X
All chips prior to GP10X do not support ZBC (Zero Bandwidth Clear) to stencil
part of the packed kinds (packed kinds refer to Z24S8 and Z32_X24S8 kinds).
Clears for these kinds typically happen in two phases, depth phase and
stencil phase. The depth clears can be compressed or ZBC-ed, whereas the
stencil part is always uncompressed.
Stencil ZBC in GP10X
For GP10X both the depth and the stencil data for these packed kinds can be
ZBC cleared. A given tile will be a cross product of the following states
for depth and stencil.
Depth: Uncompressed, 1-2 plane compressed, 3-4 plane compressed, ZBC index 0,
ZBC index 1
Stencil: Uncompressed, ZBC index 0, ZBC index 1, ZBC index 2
JIRA GV11B-9
Change-Id: I3381fd6305a4fada64211176b8ef98f27b04089f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1235520
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions