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authorAlex Waterman <alexw@nvidia.com>2017-11-16 14:29:11 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2017-11-16 18:55:52 -0500
commitb7cc3a2aa6c92a09eed43513287c9062f22ad127 (patch)
tree0943ccb3962312810ab236d98fb5ff09b8843119 /scripts/nvgpu_debug_hal.py
parent3590080109511b203e9a9187f83aef61513d3d1a (diff)
gpu: nvgpu: Fix some barrier usage
Commit 81868a187fa3b217368206f17b19309846e8e7fb updated barrier usage to use the nvgpu wrappers and in doing so downgraded many plain barriers {mb(), wmb(), rmb()} to the SMP versions of these barriers. The SMP version of the barriers in question are only issued when running on an SMP machine. In most of the cases mentioned above this is fine since the barriers are present to faciliate proper ordering across CPUs. A single CPU is always coherent with itself, so on a non-SMP case we don't need those barriers. However, there are a few places where the barriers in use (GMMU page table programming, IO accessors, userd) where the barrier usage is for communicating and establishing ordering for the GPU. We need these barriers for both SMP machines and non-SMP machines. Therefor we must use the plain barrier versions. Change-Id: I376129840b7dc64af8f3f23f88057e4e81360f89 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1599744 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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