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| author | Deepak Nibade <dnibade@nvidia.com> | 2018-04-02 09:40:42 -0400 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-04-04 14:49:46 -0400 |
| commit | 89e0745fa024891b988508c3baa20c453230a80b (patch) | |
| tree | b59efd3831570c624c9f8b611abb81489346862d /scripts/nvgpu_debug_hal.py | |
| parent | a108d3f0368c72f2d553cac1470531677b5a7b88 (diff) | |
gpu: nvgpu: handle misaligned_addr SM exception
We right now do not handle misaligned_addr SM exception explicitly and hence
we incorrectly initiate CILP on this exception
Handle this exception explicitly in this sequence -
- set error notifier first
- clear the interrupt
- return error from gr_gv11b_handle_warp_esr_error_misaligned_addr() so that
RC recovery is triggered by gk20a_gr_isr()
Ensure that the error value is propagated back to gk20a_gr_isr() correctly
Use nvgpu_set_error_notifier_if_empty() to set error notifier since this will
prevent overwriting of error notifier value in case gk20a_gr_isr() also tries
to write to some error notifier value
Bug 200388475
Jira NVGPU-554
Change-Id: I84c4d202a8068e738567ccd344e05d9d5f6ad2f0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1686781
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'scripts/nvgpu_debug_hal.py')
0 files changed, 0 insertions, 0 deletions