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authorPeter Daifuku <pdaifuku@nvidia.com>2017-03-17 14:36:19 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-03-24 12:08:17 -0400
commitfd02ab4d540ef473df1fe189653cc521876663d6 (patch)
tree1c61ea5b63900808cf79903e72a0bf462814b077 /include
parenta9fb2a4824a48f4ff193a1a54d1143ac0395aa95 (diff)
gpu: nvgpu: vgpu: profiler reservation support
Support for hwpm reservations in the virtual case: - Add session ops for checking and setting global and context reservations, and releasing reservations - in the native case, these just update reservation counts and flags - in the vgpu case, when the reservation count is 0, check with the RM server that a reservation is possible: for global reservations, no other guest can have a reservation; for context reservations, no other guest can have a global reservation - in the vgpu case, when the reservation count is decremented to 0, notify the RM server that the guest no longer has any reservations Bug 1775465 JIRA VFND-3428 Change-Id: Idf115b730e465e35d0745c96a8f8ab6b645c7cae Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1323375 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'include')
-rw-r--r--include/linux/tegra_vgpu.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h
index c0964083..bb9bdcab 100644
--- a/include/linux/tegra_vgpu.h
+++ b/include/linux/tegra_vgpu.h
@@ -102,6 +102,7 @@ enum {
102 TEGRA_VGPU_CMD_SUSPEND_CONTEXTS = 66, 102 TEGRA_VGPU_CMD_SUSPEND_CONTEXTS = 66,
103 TEGRA_VGPU_CMD_RESUME_CONTEXTS = 67, 103 TEGRA_VGPU_CMD_RESUME_CONTEXTS = 67,
104 TEGRA_VGPU_CMD_CLEAR_SM_ERROR_STATE = 68, 104 TEGRA_VGPU_CMD_CLEAR_SM_ERROR_STATE = 68,
105 TEGRA_VGPU_CMD_PROF_MGT = 72,
105}; 106};
106 107
107struct tegra_vgpu_connect_params { 108struct tegra_vgpu_connect_params {
@@ -469,6 +470,16 @@ struct tegra_vgpu_clear_sm_error_state {
469 u32 sm_id; 470 u32 sm_id;
470}; 471};
471 472
473enum {
474 TEGRA_VGPU_PROF_GET_GLOBAL = 0,
475 TEGRA_VGPU_PROF_GET_CONTEXT,
476 TEGRA_VGPU_PROF_RELEASE
477};
478
479struct tegra_vgpu_prof_mgt_params {
480 u32 mode;
481};
482
472struct tegra_vgpu_cmd_msg { 483struct tegra_vgpu_cmd_msg {
473 u32 cmd; 484 u32 cmd;
474 int ret; 485 int ret;
@@ -518,6 +529,7 @@ struct tegra_vgpu_cmd_msg {
518 struct tegra_vgpu_suspend_resume_contexts suspend_contexts; 529 struct tegra_vgpu_suspend_resume_contexts suspend_contexts;
519 struct tegra_vgpu_suspend_resume_contexts resume_contexts; 530 struct tegra_vgpu_suspend_resume_contexts resume_contexts;
520 struct tegra_vgpu_clear_sm_error_state clear_sm_error_state; 531 struct tegra_vgpu_clear_sm_error_state clear_sm_error_state;
532 struct tegra_vgpu_prof_mgt_params prof_management;
521 char padding[192]; 533 char padding[192];
522 } params; 534 } params;
523}; 535};