summaryrefslogtreecommitdiffstats
path: root/include
diff options
context:
space:
mode:
authorDeepak Nibade <dnibade@nvidia.com>2018-01-16 06:07:37 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2018-02-07 18:35:47 -0500
commitf0cbe19b12524f5df6466eaf86acbfb349def6b1 (patch)
treebed8a312e29592d41d9de4afb331756c2d38fb96 /include
parent0c8deb74aff6d0781cdf3278f56d7bce42b16a67 (diff)
gpu: nvgpu: add user API to get read-only syncpoint address map
Add User space API NVGPU_AS_IOCTL_GET_SYNC_RO_MAP to get read-only syncpoint address map in user space We already map whole syncpoint shim to each address space with base address being vm->syncpt_ro_map_gpu_va This new API exposes this base GPU_VA address of syncpoint map, and unit size of each syncpoint to user space. User space can then calculate address of each syncpoint as syncpoint_address = base_gpu_va + (syncpoint_id * syncpoint_unit_size) Note that this syncpoint address is read_only, and should be only used for inserting semaphore acquires. Adding semaphore release with this address would result in MMU_FAULT Define new HAL g->ops.fifo.get_sync_ro_map and set this for all GPUs supported on Xavier SoC Bug 200327559 Change-Id: Ica0db48fc28fdd0ff2a5eb09574dac843dc5e4fd Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1649365 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'include')
-rw-r--r--include/uapi/linux/nvgpu.h10
1 files changed, 9 insertions, 1 deletions
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h
index 6821af07..41b4eb8d 100644
--- a/include/uapi/linux/nvgpu.h
+++ b/include/uapi/linux/nvgpu.h
@@ -1968,6 +1968,12 @@ struct nvgpu_as_map_buffer_batch_args {
1968 __u64 reserved; 1968 __u64 reserved;
1969}; 1969};
1970 1970
1971struct nvgpu_as_get_sync_ro_map_args {
1972 __u64 base_gpuva;
1973 __u32 sync_size;
1974 __u32 padding;
1975};
1976
1971#define NVGPU_AS_IOCTL_BIND_CHANNEL \ 1977#define NVGPU_AS_IOCTL_BIND_CHANNEL \
1972 _IOWR(NVGPU_AS_IOCTL_MAGIC, 1, struct nvgpu_as_bind_channel_args) 1978 _IOWR(NVGPU_AS_IOCTL_MAGIC, 1, struct nvgpu_as_bind_channel_args)
1973#define NVGPU32_AS_IOCTL_ALLOC_SPACE \ 1979#define NVGPU32_AS_IOCTL_ALLOC_SPACE \
@@ -1990,9 +1996,11 @@ struct nvgpu_as_map_buffer_batch_args {
1990 _IOWR(NVGPU_AS_IOCTL_MAGIC, 10, struct nvgpu_as_map_buffer_compbits_args) 1996 _IOWR(NVGPU_AS_IOCTL_MAGIC, 10, struct nvgpu_as_map_buffer_compbits_args)
1991#define NVGPU_AS_IOCTL_MAP_BUFFER_BATCH \ 1997#define NVGPU_AS_IOCTL_MAP_BUFFER_BATCH \
1992 _IOWR(NVGPU_AS_IOCTL_MAGIC, 11, struct nvgpu_as_map_buffer_batch_args) 1998 _IOWR(NVGPU_AS_IOCTL_MAGIC, 11, struct nvgpu_as_map_buffer_batch_args)
1999#define NVGPU_AS_IOCTL_GET_SYNC_RO_MAP \
2000 _IOR(NVGPU_AS_IOCTL_MAGIC, 12, struct nvgpu_as_get_sync_ro_map_args)
1993 2001
1994#define NVGPU_AS_IOCTL_LAST \ 2002#define NVGPU_AS_IOCTL_LAST \
1995 _IOC_NR(NVGPU_AS_IOCTL_MAP_BUFFER_BATCH) 2003 _IOC_NR(NVGPU_AS_IOCTL_GET_SYNC_RO_MAP)
1996#define NVGPU_AS_IOCTL_MAX_ARG_SIZE \ 2004#define NVGPU_AS_IOCTL_MAX_ARG_SIZE \
1997 sizeof(struct nvgpu_as_map_buffer_ex_args) 2005 sizeof(struct nvgpu_as_map_buffer_ex_args)
1998 2006