diff options
author | Richard Zhao <rizhao@nvidia.com> | 2016-12-28 19:28:11 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-01-06 18:02:24 -0500 |
commit | e229514bece5a109cdbfe263f6329efe987e5939 (patch) | |
tree | 5900d1bcf0067e1109ebfe1666f9ae19239c4006 /include | |
parent | ecc3722aa1d7cd439035b0895781930871008a82 (diff) |
gpu: nvgpu: vgpu: receive event TEGRA_VGPU_EVENT_SM_ESR
- allocate gr.sm_error_state
- handle event of sm error state
- add callback of clear sm error state
JIRA VFND-3291
Bug 200257899
Change-Id: I49b9437013e8c65290750b7fe21fc6819ea93b1c
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1278397
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'include')
-rw-r--r-- | include/linux/tegra_vgpu.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h index 40f92aec..14449242 100644 --- a/include/linux/tegra_vgpu.h +++ b/include/linux/tegra_vgpu.h | |||
@@ -560,6 +560,15 @@ struct tegra_vgpu_channel_event_info { | |||
560 | u32 id; /* channel id or tsg id */ | 560 | u32 id; /* channel id or tsg id */ |
561 | }; | 561 | }; |
562 | 562 | ||
563 | struct tegra_vgpu_sm_esr_info { | ||
564 | u32 sm_id; | ||
565 | u32 hww_global_esr; | ||
566 | u32 hww_warp_esr; | ||
567 | u64 hww_warp_esr_pc; | ||
568 | u32 hww_global_esr_report_mask; | ||
569 | u32 hww_warp_esr_report_mask; | ||
570 | }; | ||
571 | |||
563 | enum { | 572 | enum { |
564 | 573 | ||
565 | TEGRA_VGPU_INTR_GR = 0, | 574 | TEGRA_VGPU_INTR_GR = 0, |
@@ -575,6 +584,7 @@ enum { | |||
575 | TEGRA_VGPU_EVENT_ABORT = 1, | 584 | TEGRA_VGPU_EVENT_ABORT = 1, |
576 | TEGRA_VGPU_EVENT_FECS_TRACE = 2, | 585 | TEGRA_VGPU_EVENT_FECS_TRACE = 2, |
577 | TEGRA_VGPU_EVENT_CHANNEL = 3, | 586 | TEGRA_VGPU_EVENT_CHANNEL = 3, |
587 | TEGRA_VGPU_EVENT_SM_ESR = 4, | ||
578 | }; | 588 | }; |
579 | 589 | ||
580 | struct tegra_vgpu_intr_msg { | 590 | struct tegra_vgpu_intr_msg { |
@@ -588,6 +598,7 @@ struct tegra_vgpu_intr_msg { | |||
588 | struct tegra_vgpu_ce2_nonstall_intr_info ce2_nonstall_intr; | 598 | struct tegra_vgpu_ce2_nonstall_intr_info ce2_nonstall_intr; |
589 | struct tegra_vgpu_fecs_trace_event_info fecs_trace; | 599 | struct tegra_vgpu_fecs_trace_event_info fecs_trace; |
590 | struct tegra_vgpu_channel_event_info channel_event; | 600 | struct tegra_vgpu_channel_event_info channel_event; |
601 | struct tegra_vgpu_sm_esr_info sm_esr; | ||
591 | char padding[32]; | 602 | char padding[32]; |
592 | } info; | 603 | } info; |
593 | }; | 604 | }; |