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authorVaibhav Kachore <vkachore@nvidia.com>2018-07-06 05:40:03 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-07-10 21:13:43 -0400
commite14fdcd8f1f4125da697433b1744b1e4e4f15b09 (patch)
treef48ff794ef77e977ccba397f5abf14f5ae7b185b /include
parent4cd59404a2d4ab1c31605d96cff848dd4e93c3b4 (diff)
gpu: nvgpu: enable HWPM Mode-E context switch
- Write new pm mode to context buffer header. Ucode use this mode to enable mode-e context switch. This is Mode-B context switch of PMs with Mode-E streamout on one context. If this mode is set, Ucode makes sure that Mode-E pipe (perfmons, routers, pma) is idle before it context switches PMs. - This allows us to collect counters in a secure way (i.e. on context basis) with stream out. Bug 2106999 Change-Id: I5a7435f09d1bf053ca428e538b0a57f3a175ac37 Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1760366 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'include')
-rw-r--r--include/uapi/linux/nvgpu.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h
index b85ca7b6..446f5bd3 100644
--- a/include/uapi/linux/nvgpu.h
+++ b/include/uapi/linux/nvgpu.h
@@ -1286,8 +1286,12 @@ struct nvgpu_dbg_gpu_set_next_stop_trigger_type_args {
1286 1286
1287 1287
1288/* PM Context Switch Mode */ 1288/* PM Context Switch Mode */
1289/*This mode says that the pms are not to be context switched. */
1289#define NVGPU_DBG_GPU_HWPM_CTXSW_MODE_NO_CTXSW (0x00000000) 1290#define NVGPU_DBG_GPU_HWPM_CTXSW_MODE_NO_CTXSW (0x00000000)
1291/* This mode says that the pms in Mode-B are to be context switched */
1290#define NVGPU_DBG_GPU_HWPM_CTXSW_MODE_CTXSW (0x00000001) 1292#define NVGPU_DBG_GPU_HWPM_CTXSW_MODE_CTXSW (0x00000001)
1293/* This mode says that the pms in Mode-E (stream out) are to be context switched. */
1294#define NVGPU_DBG_GPU_HWPM_CTXSW_MODE_STREAM_OUT_CTXSW (0x00000002)
1291 1295
1292struct nvgpu_dbg_gpu_hwpm_ctxsw_mode_args { 1296struct nvgpu_dbg_gpu_hwpm_ctxsw_mode_args {
1293 __u32 mode; 1297 __u32 mode;