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| author | Seema Khowala <seemaj@nvidia.com> | 2017-03-21 14:17:48 -0400 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-03-23 12:34:18 -0400 |
| commit | df94d474a8200fc61969e2fc35d1b2a8d7fa5b8c (patch) | |
| tree | d86e44d6263d48579346293aaeff7f5b2f826899 /include | |
| parent | 4492c62ffe9398bd4457f6f1c2773e40afe909fb (diff) | |
gpu: nvgpu: add init_pbdma_intr_desc fifo ops
Init device_fatal, channel_fatal and restartable fifo intr pbdma s/w
variables for pbdma_intr_0 interrupt masks for each GPU version separately
pbdma_intr_0 field differences for each GPU version:-
-gk20a : bit 28 does not exists in hw
-gm20b : bit 8(lbreq), 20(xbarconnect) and 28 do not exist in hw
-gp10b : bit 8(lbreq), 20(xbarconnect) do not exist in hw. bit 28,
(syncpoint_illegal) added in hw but is not being handled.
-gk20a/gm20b/gp10b
bit 24 eng_reset and bit 25 semaphore always existed in hw but never
handled
JIRA GPUT19X-47
Change-Id: I209191f57c5ea5b15081b7dc2411801d3537017c
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1325402
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions