diff options
author | Richard Zhao <rizhao@nvidia.com> | 2016-03-31 14:16:23 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-05-31 13:47:22 -0400 |
commit | d707c5a444e024e1184213a75f44a73dbb1707d2 (patch) | |
tree | 09711370df9d9078e4f604e60983877bbf30b9de /include | |
parent | a71ce831fbbca3ba8602e0b07ecd630c4a39f376 (diff) |
gpu: nvgpu: add tsg support for vgpu
- make tsg_gk20a.c call HAL for enable/disable channels
- add preempt_tsg HAL callbacks
- add tsg bind/unbind channel HAL callbacks
- add according tsg callbacks for vgpu
Bug 1702773
JIRA VFND-1003
Change-Id: I2cba74b3ebd3920ef09219a168e6433d9574dbe8
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1144932
(cherry picked from commit c3787de7d38651d46969348f5acae2ba86b31ec7)
Reviewed-on: http://git-master/r/1126942
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'include')
-rw-r--r-- | include/linux/tegra_vgpu.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h index 1d195efd..bdaabf29 100644 --- a/include/linux/tegra_vgpu.h +++ b/include/linux/tegra_vgpu.h | |||
@@ -88,6 +88,9 @@ enum { | |||
88 | TEGRA_VGPU_CMD_GR_CTX_FREE, | 88 | TEGRA_VGPU_CMD_GR_CTX_FREE, |
89 | TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTX, | 89 | TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTX, |
90 | TEGRA_VGPU_CMD_TSG_BIND_GR_CTX, | 90 | TEGRA_VGPU_CMD_TSG_BIND_GR_CTX, |
91 | TEGRA_VGPU_CMD_TSG_BIND_CHANNEL, | ||
92 | TEGRA_VGPU_CMD_TSG_UNBIND_CHANNEL, | ||
93 | TEGRA_VGPU_CMD_TSG_PREEMPT, | ||
91 | }; | 94 | }; |
92 | 95 | ||
93 | struct tegra_vgpu_connect_params { | 96 | struct tegra_vgpu_connect_params { |
@@ -361,6 +364,15 @@ struct tegra_vgpu_tsg_bind_gr_ctx_params { | |||
361 | u64 gr_ctx_handle; | 364 | u64 gr_ctx_handle; |
362 | }; | 365 | }; |
363 | 366 | ||
367 | struct tegra_vgpu_tsg_bind_unbind_channel_params { | ||
368 | u32 tsg_id; | ||
369 | u64 ch_handle; | ||
370 | }; | ||
371 | |||
372 | struct tegra_vgpu_tsg_preempt_params { | ||
373 | u32 tsg_id; | ||
374 | }; | ||
375 | |||
364 | struct tegra_vgpu_cmd_msg { | 376 | struct tegra_vgpu_cmd_msg { |
365 | u32 cmd; | 377 | u32 cmd; |
366 | int ret; | 378 | int ret; |
@@ -397,6 +409,8 @@ struct tegra_vgpu_cmd_msg { | |||
397 | struct tegra_vgpu_gr_ctx_params gr_ctx; | 409 | struct tegra_vgpu_gr_ctx_params gr_ctx; |
398 | struct tegra_vgpu_channel_bind_gr_ctx_params ch_bind_gr_ctx; | 410 | struct tegra_vgpu_channel_bind_gr_ctx_params ch_bind_gr_ctx; |
399 | struct tegra_vgpu_tsg_bind_gr_ctx_params tsg_bind_gr_ctx; | 411 | struct tegra_vgpu_tsg_bind_gr_ctx_params tsg_bind_gr_ctx; |
412 | struct tegra_vgpu_tsg_bind_unbind_channel_params tsg_bind_unbind_channel; | ||
413 | struct tegra_vgpu_tsg_preempt_params tsg_preempt; | ||
400 | char padding[192]; | 414 | char padding[192]; |
401 | } params; | 415 | } params; |
402 | }; | 416 | }; |