diff options
author | Richard Zhao <rizhao@nvidia.com> | 2018-01-26 21:07:51 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-02-27 17:30:01 -0500 |
commit | c45462288d09955b2a163274d501c4d0aa10a74b (patch) | |
tree | fb76c9472df4b10af854d1c3a1e1159a846648dd /include | |
parent | 5025350b80f4ded30d6ab2ed3590c6a61937eef7 (diff) |
gpu: nvgpu: vgpu: move tegra_vgpu.h to include/nvgpu/vgpu/
tegra_vgpu.h is os agnostic, so move it out of linux folder.
Jira EVLR-2364
Change-Id: Ibbe8923f7af036b3b6730f682f5243ca73810f7b
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1649936
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nirav Patel <nipatel@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'include')
-rw-r--r-- | include/linux/tegra_vgpu.h | 738 |
1 files changed, 0 insertions, 738 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h deleted file mode 100644 index 9980f4bc..00000000 --- a/include/linux/tegra_vgpu.h +++ /dev/null | |||
@@ -1,738 +0,0 @@ | |||
1 | /* | ||
2 | * Tegra GPU Virtualization Interfaces to Server | ||
3 | * | ||
4 | * Copyright (c) 2014-2018, NVIDIA Corporation. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
17 | */ | ||
18 | |||
19 | #ifndef __TEGRA_VGPU_H | ||
20 | #define __TEGRA_VGPU_H | ||
21 | |||
22 | #include <nvgpu/types.h> | ||
23 | |||
24 | enum { | ||
25 | TEGRA_VGPU_MODULE_GPU = 0, | ||
26 | }; | ||
27 | |||
28 | enum { | ||
29 | /* Needs to follow last entry in TEGRA_VHOST_QUEUE_* list, | ||
30 | * in tegra_vhost.h | ||
31 | */ | ||
32 | TEGRA_VGPU_QUEUE_CMD = 3, | ||
33 | TEGRA_VGPU_QUEUE_INTR | ||
34 | }; | ||
35 | |||
36 | enum { | ||
37 | TEGRA_VGPU_CMD_CONNECT = 0, | ||
38 | TEGRA_VGPU_CMD_DISCONNECT = 1, | ||
39 | TEGRA_VGPU_CMD_ABORT = 2, | ||
40 | TEGRA_VGPU_CMD_CHANNEL_ALLOC_HWCTX = 3, | ||
41 | TEGRA_VGPU_CMD_CHANNEL_FREE_HWCTX = 4, | ||
42 | TEGRA_VGPU_CMD_GET_ATTRIBUTE = 5, | ||
43 | TEGRA_VGPU_CMD_MAP_BAR1 = 6, | ||
44 | TEGRA_VGPU_CMD_AS_ALLOC_SHARE = 7, | ||
45 | TEGRA_VGPU_CMD_AS_BIND_SHARE = 8, | ||
46 | TEGRA_VGPU_CMD_AS_FREE_SHARE = 9, | ||
47 | TEGRA_VGPU_CMD_AS_MAP = 10, | ||
48 | TEGRA_VGPU_CMD_AS_UNMAP = 11, | ||
49 | TEGRA_VGPU_CMD_CHANNEL_BIND = 13, | ||
50 | TEGRA_VGPU_CMD_CHANNEL_UNBIND = 14, | ||
51 | TEGRA_VGPU_CMD_CHANNEL_DISABLE = 15, | ||
52 | TEGRA_VGPU_CMD_CHANNEL_PREEMPT = 16, | ||
53 | TEGRA_VGPU_CMD_CHANNEL_SETUP_RAMFC = 17, | ||
54 | TEGRA_VGPU_CMD_CHANNEL_COMMIT_GR_CTX = 20, | ||
55 | TEGRA_VGPU_CMD_CHANNEL_ALLOC_GR_PATCH_CTX = 21, | ||
56 | TEGRA_VGPU_CMD_CHANNEL_FREE_GR_PATCH_CTX = 22, | ||
57 | TEGRA_VGPU_CMD_CHANNEL_MAP_GR_GLOBAL_CTX = 23, | ||
58 | TEGRA_VGPU_CMD_CHANNEL_UNMAP_GR_GLOBAL_CTX = 24, | ||
59 | TEGRA_VGPU_CMD_CHANNEL_COMMIT_GR_GLOBAL_CTX = 25, | ||
60 | TEGRA_VGPU_CMD_CHANNEL_LOAD_GR_GOLDEN_CTX = 26, | ||
61 | TEGRA_VGPU_CMD_CHANNEL_BIND_ZCULL = 27, | ||
62 | TEGRA_VGPU_CMD_CACHE_MAINT = 28, | ||
63 | TEGRA_VGPU_CMD_SUBMIT_RUNLIST = 29, | ||
64 | TEGRA_VGPU_CMD_GET_ZCULL_INFO = 30, | ||
65 | TEGRA_VGPU_CMD_ZBC_SET_TABLE = 31, | ||
66 | TEGRA_VGPU_CMD_ZBC_QUERY_TABLE = 32, | ||
67 | TEGRA_VGPU_CMD_AS_MAP_EX = 33, | ||
68 | TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS = 34, | ||
69 | TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE = 35, | ||
70 | TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE = 36, | ||
71 | TEGRA_VGPU_CMD_REG_OPS = 37, | ||
72 | TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY = 38, | ||
73 | TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE = 39, | ||
74 | TEGRA_VGPU_CMD_CHANNEL_SET_TIMESLICE = 40, | ||
75 | TEGRA_VGPU_CMD_FECS_TRACE_ENABLE = 41, | ||
76 | TEGRA_VGPU_CMD_FECS_TRACE_DISABLE = 42, | ||
77 | TEGRA_VGPU_CMD_FECS_TRACE_POLL = 43, | ||
78 | TEGRA_VGPU_CMD_FECS_TRACE_SET_FILTER = 44, | ||
79 | TEGRA_VGPU_CMD_CHANNEL_SET_SMPC_CTXSW_MODE = 45, | ||
80 | TEGRA_VGPU_CMD_CHANNEL_SET_HWPM_CTXSW_MODE = 46, | ||
81 | TEGRA_VGPU_CMD_CHANNEL_FREE_HWPM_CTX = 47, | ||
82 | TEGRA_VGPU_CMD_GR_CTX_ALLOC = 48, | ||
83 | TEGRA_VGPU_CMD_GR_CTX_FREE = 49, | ||
84 | TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTX =50, | ||
85 | TEGRA_VGPU_CMD_TSG_BIND_GR_CTX = 51, | ||
86 | TEGRA_VGPU_CMD_TSG_BIND_CHANNEL = 52, | ||
87 | TEGRA_VGPU_CMD_TSG_UNBIND_CHANNEL = 53, | ||
88 | TEGRA_VGPU_CMD_TSG_PREEMPT = 54, | ||
89 | TEGRA_VGPU_CMD_TSG_SET_TIMESLICE = 55, | ||
90 | TEGRA_VGPU_CMD_TSG_SET_RUNLIST_INTERLEAVE = 56, | ||
91 | TEGRA_VGPU_CMD_CHANNEL_FORCE_RESET = 57, | ||
92 | TEGRA_VGPU_CMD_CHANNEL_ENABLE = 58, | ||
93 | TEGRA_VGPU_CMD_READ_PTIMER = 59, | ||
94 | TEGRA_VGPU_CMD_SET_POWERGATE = 60, | ||
95 | TEGRA_VGPU_CMD_SET_GPU_CLK_RATE = 61, | ||
96 | TEGRA_VGPU_CMD_GET_CONSTANTS = 62, | ||
97 | TEGRA_VGPU_CMD_CHANNEL_CYCLESTATS_SNAPSHOT = 63, | ||
98 | TEGRA_VGPU_CMD_TSG_OPEN = 64, | ||
99 | TEGRA_VGPU_CMD_GET_GPU_LOAD = 65, | ||
100 | TEGRA_VGPU_CMD_SUSPEND_CONTEXTS = 66, | ||
101 | TEGRA_VGPU_CMD_RESUME_CONTEXTS = 67, | ||
102 | TEGRA_VGPU_CMD_CLEAR_SM_ERROR_STATE = 68, | ||
103 | TEGRA_VGPU_CMD_GET_GPU_CLK_RATE = 69, | ||
104 | TEGRA_VGPU_CMD_GET_GPU_FREQ_TABLE = 70, | ||
105 | TEGRA_VGPU_CMD_CAP_GPU_CLK_RATE = 71, | ||
106 | TEGRA_VGPU_CMD_PROF_MGT = 72, | ||
107 | TEGRA_VGPU_CMD_PERFBUF_MGT = 73, | ||
108 | TEGRA_VGPU_CMD_GET_TIMESTAMPS_ZIPPER = 74, | ||
109 | TEGRA_VGPU_CMD_TSG_RELEASE = 75, | ||
110 | TEGRA_VGPU_CMD_GET_VSMS_MAPPING = 76, | ||
111 | TEGRA_VGPU_CMD_ALLOC_CTX_HEADER = 77, | ||
112 | TEGRA_VGPU_CMD_FREE_CTX_HEADER = 78, | ||
113 | TEGRA_VGPU_CMD_MAP_SYNCPT = 79, | ||
114 | TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX = 80, | ||
115 | }; | ||
116 | |||
117 | struct tegra_vgpu_connect_params { | ||
118 | u32 module; | ||
119 | u64 handle; | ||
120 | }; | ||
121 | |||
122 | struct tegra_vgpu_channel_hwctx_params { | ||
123 | u32 id; | ||
124 | u64 pid; | ||
125 | u64 handle; | ||
126 | }; | ||
127 | |||
128 | struct tegra_vgpu_attrib_params { | ||
129 | u32 attrib; | ||
130 | u32 value; | ||
131 | }; | ||
132 | |||
133 | struct tegra_vgpu_as_share_params { | ||
134 | u64 size; | ||
135 | u64 handle; | ||
136 | u32 big_page_size; | ||
137 | }; | ||
138 | |||
139 | struct tegra_vgpu_as_bind_share_params { | ||
140 | u64 as_handle; | ||
141 | u64 chan_handle; | ||
142 | }; | ||
143 | |||
144 | enum { | ||
145 | TEGRA_VGPU_MAP_PROT_NONE = 0, | ||
146 | TEGRA_VGPU_MAP_PROT_READ_ONLY, | ||
147 | TEGRA_VGPU_MAP_PROT_WRITE_ONLY | ||
148 | }; | ||
149 | |||
150 | struct tegra_vgpu_as_map_params { | ||
151 | u64 handle; | ||
152 | u64 addr; | ||
153 | u64 gpu_va; | ||
154 | u64 size; | ||
155 | u8 pgsz_idx; | ||
156 | u8 iova; | ||
157 | u8 kind; | ||
158 | u8 cacheable; | ||
159 | u8 clear_ctags; | ||
160 | u8 prot; | ||
161 | u32 ctag_offset; | ||
162 | }; | ||
163 | |||
164 | #define TEGRA_VGPU_MAP_CACHEABLE (1 << 0) | ||
165 | #define TEGRA_VGPU_MAP_IO_COHERENT (1 << 1) | ||
166 | #define TEGRA_VGPU_MAP_L3_ALLOC (1 << 2) | ||
167 | |||
168 | struct tegra_vgpu_as_map_ex_params { | ||
169 | u64 handle; | ||
170 | u64 gpu_va; | ||
171 | u64 size; | ||
172 | u32 mem_desc_count; | ||
173 | u8 pgsz_idx; | ||
174 | u8 iova; | ||
175 | u8 kind; | ||
176 | u32 flags; | ||
177 | u8 clear_ctags; | ||
178 | u8 prot; | ||
179 | u32 ctag_offset; | ||
180 | }; | ||
181 | |||
182 | struct tegra_vgpu_mem_desc { | ||
183 | u64 addr; | ||
184 | u64 length; | ||
185 | }; | ||
186 | |||
187 | struct tegra_vgpu_channel_config_params { | ||
188 | u64 handle; | ||
189 | }; | ||
190 | |||
191 | struct tegra_vgpu_ramfc_params { | ||
192 | u64 handle; | ||
193 | u64 gpfifo_va; | ||
194 | u32 num_entries; | ||
195 | u64 userd_addr; | ||
196 | u8 iova; | ||
197 | }; | ||
198 | |||
199 | struct tegra_vgpu_ch_ctx_params { | ||
200 | u64 handle; | ||
201 | u64 gr_ctx_va; | ||
202 | u64 patch_ctx_va; | ||
203 | u64 cb_va; | ||
204 | u64 attr_va; | ||
205 | u64 page_pool_va; | ||
206 | u64 priv_access_map_va; | ||
207 | u32 class_num; | ||
208 | }; | ||
209 | |||
210 | struct tegra_vgpu_zcull_bind_params { | ||
211 | u64 handle; | ||
212 | u64 zcull_va; | ||
213 | u32 mode; | ||
214 | }; | ||
215 | |||
216 | enum { | ||
217 | TEGRA_VGPU_L2_MAINT_FLUSH = 0, | ||
218 | TEGRA_VGPU_L2_MAINT_INV, | ||
219 | TEGRA_VGPU_L2_MAINT_FLUSH_INV, | ||
220 | TEGRA_VGPU_FB_FLUSH | ||
221 | }; | ||
222 | |||
223 | struct tegra_vgpu_cache_maint_params { | ||
224 | u8 op; | ||
225 | }; | ||
226 | |||
227 | struct tegra_vgpu_runlist_params { | ||
228 | u8 runlist_id; | ||
229 | u32 num_entries; | ||
230 | }; | ||
231 | |||
232 | struct tegra_vgpu_golden_ctx_params { | ||
233 | u32 size; | ||
234 | }; | ||
235 | |||
236 | struct tegra_vgpu_zcull_info_params { | ||
237 | u32 width_align_pixels; | ||
238 | u32 height_align_pixels; | ||
239 | u32 pixel_squares_by_aliquots; | ||
240 | u32 aliquot_total; | ||
241 | u32 region_byte_multiplier; | ||
242 | u32 region_header_size; | ||
243 | u32 subregion_header_size; | ||
244 | u32 subregion_width_align_pixels; | ||
245 | u32 subregion_height_align_pixels; | ||
246 | u32 subregion_count; | ||
247 | }; | ||
248 | |||
249 | #define TEGRA_VGPU_ZBC_COLOR_VALUE_SIZE 4 | ||
250 | #define TEGRA_VGPU_ZBC_TYPE_INVALID 0 | ||
251 | #define TEGRA_VGPU_ZBC_TYPE_COLOR 1 | ||
252 | #define TEGRA_VGPU_ZBC_TYPE_DEPTH 2 | ||
253 | |||
254 | struct tegra_vgpu_zbc_set_table_params { | ||
255 | u32 color_ds[TEGRA_VGPU_ZBC_COLOR_VALUE_SIZE]; | ||
256 | u32 color_l2[TEGRA_VGPU_ZBC_COLOR_VALUE_SIZE]; | ||
257 | u32 depth; | ||
258 | u32 format; | ||
259 | u32 type; /* color or depth */ | ||
260 | }; | ||
261 | |||
262 | struct tegra_vgpu_zbc_query_table_params { | ||
263 | u32 color_ds[TEGRA_VGPU_ZBC_COLOR_VALUE_SIZE]; | ||
264 | u32 color_l2[TEGRA_VGPU_ZBC_COLOR_VALUE_SIZE]; | ||
265 | u32 depth; | ||
266 | u32 ref_cnt; | ||
267 | u32 format; | ||
268 | u32 type; /* color or depth */ | ||
269 | u32 index_size; /* [out] size, [in] index */ | ||
270 | }; | ||
271 | |||
272 | enum { | ||
273 | TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN, | ||
274 | TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL, | ||
275 | TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL, | ||
276 | TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB, | ||
277 | TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_LAST | ||
278 | }; | ||
279 | |||
280 | enum { | ||
281 | TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_WFI, | ||
282 | TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_GFX_GFXP, | ||
283 | TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CTA, | ||
284 | TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CILP, | ||
285 | TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_LAST | ||
286 | }; | ||
287 | |||
288 | struct tegra_vgpu_gr_bind_ctxsw_buffers_params { | ||
289 | u64 handle; /* deprecated */ | ||
290 | u64 gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_LAST]; | ||
291 | u64 size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_LAST]; | ||
292 | u32 mode; | ||
293 | u64 gr_ctx_handle; | ||
294 | }; | ||
295 | |||
296 | struct tegra_vgpu_mmu_debug_mode { | ||
297 | u32 enable; | ||
298 | }; | ||
299 | |||
300 | struct tegra_vgpu_sm_debug_mode { | ||
301 | u64 handle; | ||
302 | u64 sms; | ||
303 | u32 enable; | ||
304 | }; | ||
305 | |||
306 | struct tegra_vgpu_reg_op { | ||
307 | u8 op; | ||
308 | u8 type; | ||
309 | u8 status; | ||
310 | u8 quad; | ||
311 | u32 group_mask; | ||
312 | u32 sub_group_mask; | ||
313 | u32 offset; | ||
314 | u32 value_lo; | ||
315 | u32 value_hi; | ||
316 | u32 and_n_mask_lo; | ||
317 | u32 and_n_mask_hi; | ||
318 | }; | ||
319 | |||
320 | struct tegra_vgpu_reg_ops_params { | ||
321 | u64 handle; | ||
322 | u64 num_ops; | ||
323 | u32 is_profiler; | ||
324 | }; | ||
325 | |||
326 | struct tegra_vgpu_channel_priority_params { | ||
327 | u64 handle; | ||
328 | u32 priority; | ||
329 | }; | ||
330 | |||
331 | /* level follows nvgpu.h definitions */ | ||
332 | struct tegra_vgpu_channel_runlist_interleave_params { | ||
333 | u64 handle; | ||
334 | u32 level; | ||
335 | }; | ||
336 | |||
337 | struct tegra_vgpu_channel_timeslice_params { | ||
338 | u64 handle; | ||
339 | u32 timeslice_us; | ||
340 | }; | ||
341 | |||
342 | #define TEGRA_VGPU_FECS_TRACE_FILTER_SIZE 256 | ||
343 | struct tegra_vgpu_fecs_trace_filter { | ||
344 | u64 tag_bits[(TEGRA_VGPU_FECS_TRACE_FILTER_SIZE + 63) / 64]; | ||
345 | }; | ||
346 | |||
347 | enum { | ||
348 | TEGRA_VGPU_CTXSW_MODE_NO_CTXSW = 0, | ||
349 | TEGRA_VGPU_CTXSW_MODE_CTXSW, | ||
350 | }; | ||
351 | |||
352 | struct tegra_vgpu_channel_set_ctxsw_mode { | ||
353 | u64 handle; | ||
354 | u64 gpu_va; | ||
355 | u32 mode; | ||
356 | }; | ||
357 | |||
358 | struct tegra_vgpu_channel_free_hwpm_ctx { | ||
359 | u64 handle; | ||
360 | }; | ||
361 | |||
362 | struct tegra_vgpu_gr_ctx_params { | ||
363 | u64 gr_ctx_handle; | ||
364 | u64 as_handle; | ||
365 | u64 gr_ctx_va; | ||
366 | u32 class_num; | ||
367 | }; | ||
368 | |||
369 | struct tegra_vgpu_channel_bind_gr_ctx_params { | ||
370 | u64 ch_handle; | ||
371 | u64 gr_ctx_handle; | ||
372 | }; | ||
373 | |||
374 | struct tegra_vgpu_tsg_bind_gr_ctx_params { | ||
375 | u32 tsg_id; | ||
376 | u64 gr_ctx_handle; | ||
377 | }; | ||
378 | |||
379 | struct tegra_vgpu_tsg_bind_unbind_channel_params { | ||
380 | u32 tsg_id; | ||
381 | u64 ch_handle; | ||
382 | }; | ||
383 | |||
384 | struct tegra_vgpu_tsg_preempt_params { | ||
385 | u32 tsg_id; | ||
386 | }; | ||
387 | |||
388 | struct tegra_vgpu_tsg_timeslice_params { | ||
389 | u32 tsg_id; | ||
390 | u32 timeslice_us; | ||
391 | }; | ||
392 | |||
393 | struct tegra_vgpu_tsg_open_rel_params { | ||
394 | u32 tsg_id; | ||
395 | }; | ||
396 | |||
397 | /* level follows nvgpu.h definitions */ | ||
398 | struct tegra_vgpu_tsg_runlist_interleave_params { | ||
399 | u32 tsg_id; | ||
400 | u32 level; | ||
401 | }; | ||
402 | |||
403 | struct tegra_vgpu_read_ptimer_params { | ||
404 | u64 time; | ||
405 | }; | ||
406 | |||
407 | #define TEGRA_VGPU_GET_TIMESTAMPS_ZIPPER_MAX_COUNT 16 | ||
408 | #define TEGRA_VGPU_GET_TIMESTAMPS_ZIPPER_SRC_ID_TSC 1 | ||
409 | struct tegra_vgpu_get_timestamps_zipper_params { | ||
410 | /* timestamp pairs */ | ||
411 | struct { | ||
412 | /* gpu timestamp value */ | ||
413 | u64 cpu_timestamp; | ||
414 | /* raw GPU counter (PTIMER) value */ | ||
415 | u64 gpu_timestamp; | ||
416 | } samples[TEGRA_VGPU_GET_TIMESTAMPS_ZIPPER_MAX_COUNT]; | ||
417 | /* number of pairs to read */ | ||
418 | u32 count; | ||
419 | /* cpu clock source id */ | ||
420 | u32 source_id; | ||
421 | }; | ||
422 | |||
423 | struct tegra_vgpu_set_powergate_params { | ||
424 | u32 mode; | ||
425 | }; | ||
426 | |||
427 | struct tegra_vgpu_gpu_clk_rate_params { | ||
428 | u32 rate; /* in kHz */ | ||
429 | }; | ||
430 | |||
431 | /* TEGRA_VGPU_MAX_ENGINES must be equal or greater than num_engines */ | ||
432 | #define TEGRA_VGPU_MAX_ENGINES 4 | ||
433 | struct tegra_vgpu_engines_info { | ||
434 | u32 num_engines; | ||
435 | struct engineinfo { | ||
436 | u32 engine_id; | ||
437 | u32 intr_mask; | ||
438 | u32 reset_mask; | ||
439 | u32 runlist_id; | ||
440 | u32 pbdma_id; | ||
441 | u32 inst_id; | ||
442 | u32 pri_base; | ||
443 | u32 engine_enum; | ||
444 | u32 fault_id; | ||
445 | } info[TEGRA_VGPU_MAX_ENGINES]; | ||
446 | }; | ||
447 | |||
448 | #define TEGRA_VGPU_MAX_GPC_COUNT 16 | ||
449 | #define TEGRA_VGPU_MAX_TPC_COUNT_PER_GPC 16 | ||
450 | |||
451 | struct tegra_vgpu_constants_params { | ||
452 | u32 arch; | ||
453 | u32 impl; | ||
454 | u32 rev; | ||
455 | u32 max_freq; | ||
456 | u32 num_channels; | ||
457 | u32 golden_ctx_size; | ||
458 | u32 zcull_ctx_size; | ||
459 | u32 l2_size; | ||
460 | u32 ltc_count; | ||
461 | u32 cacheline_size; | ||
462 | u32 slices_per_ltc; | ||
463 | u32 comptags_per_cacheline; | ||
464 | u32 comptag_lines; | ||
465 | u32 sm_arch_sm_version; | ||
466 | u32 sm_arch_spa_version; | ||
467 | u32 sm_arch_warp_count; | ||
468 | u32 max_gpc_count; | ||
469 | u32 gpc_count; | ||
470 | u32 max_tpc_per_gpc_count; | ||
471 | u32 num_fbps; | ||
472 | u32 fbp_en_mask; | ||
473 | u32 ltc_per_fbp; | ||
474 | u32 max_lts_per_ltc; | ||
475 | u8 gpc_tpc_count[TEGRA_VGPU_MAX_GPC_COUNT]; | ||
476 | /* mask bits should be equal or larger than | ||
477 | * TEGRA_VGPU_MAX_TPC_COUNT_PER_GPC | ||
478 | */ | ||
479 | u16 gpc_tpc_mask[TEGRA_VGPU_MAX_GPC_COUNT]; | ||
480 | u32 hwpm_ctx_size; | ||
481 | u8 force_preempt_mode; | ||
482 | u32 default_timeslice_us; | ||
483 | u32 preempt_ctx_size; | ||
484 | u32 channel_base; | ||
485 | struct tegra_vgpu_engines_info engines_info; | ||
486 | u32 num_pce; | ||
487 | u32 sm_per_tpc; | ||
488 | u32 max_subctx_count; | ||
489 | }; | ||
490 | |||
491 | struct tegra_vgpu_channel_cyclestats_snapshot_params { | ||
492 | u64 handle; | ||
493 | u32 perfmon_start; | ||
494 | u32 perfmon_count; | ||
495 | u32 buf_info; /* client->srvr: get ptr; srvr->client: num pending */ | ||
496 | u8 subcmd; | ||
497 | u8 hw_overflow; | ||
498 | }; | ||
499 | |||
500 | struct tegra_vgpu_gpu_load_params { | ||
501 | u32 load; | ||
502 | }; | ||
503 | |||
504 | struct tegra_vgpu_suspend_resume_contexts { | ||
505 | u32 num_channels; | ||
506 | u16 resident_chid; | ||
507 | }; | ||
508 | |||
509 | struct tegra_vgpu_clear_sm_error_state { | ||
510 | u64 handle; | ||
511 | u32 sm_id; | ||
512 | }; | ||
513 | |||
514 | enum { | ||
515 | TEGRA_VGPU_PROF_GET_GLOBAL = 0, | ||
516 | TEGRA_VGPU_PROF_GET_CONTEXT, | ||
517 | TEGRA_VGPU_PROF_RELEASE | ||
518 | }; | ||
519 | |||
520 | struct tegra_vgpu_prof_mgt_params { | ||
521 | u32 mode; | ||
522 | }; | ||
523 | |||
524 | struct tegra_vgpu_perfbuf_mgt_params { | ||
525 | u64 vm_handle; | ||
526 | u64 offset; | ||
527 | u32 size; | ||
528 | }; | ||
529 | |||
530 | #define TEGRA_VGPU_GPU_FREQ_TABLE_SIZE 25 | ||
531 | |||
532 | struct tegra_vgpu_get_gpu_freq_table_params { | ||
533 | u32 num_freqs; | ||
534 | u32 freqs[TEGRA_VGPU_GPU_FREQ_TABLE_SIZE]; /* in kHz */ | ||
535 | }; | ||
536 | |||
537 | struct tegra_vgpu_vsms_mapping_params { | ||
538 | u32 num_sm; | ||
539 | }; | ||
540 | |||
541 | struct tegra_vgpu_vsms_mapping_entry { | ||
542 | u32 gpc_index; | ||
543 | u32 tpc_index; | ||
544 | u32 sm_index; | ||
545 | u32 global_tpc_index; | ||
546 | }; | ||
547 | |||
548 | struct tegra_vgpu_alloc_ctx_header_params { | ||
549 | u64 ch_handle; | ||
550 | u64 ctx_header_va; | ||
551 | }; | ||
552 | |||
553 | struct tegra_vgpu_free_ctx_header_params { | ||
554 | u64 ch_handle; | ||
555 | }; | ||
556 | |||
557 | struct tegra_vgpu_map_syncpt_params { | ||
558 | u64 as_handle; | ||
559 | u64 gpu_va; | ||
560 | u64 len; | ||
561 | u64 offset; | ||
562 | u8 prot; | ||
563 | }; | ||
564 | |||
565 | struct tegra_vgpu_tsg_bind_channel_ex_params { | ||
566 | u32 tsg_id; | ||
567 | u64 ch_handle; | ||
568 | u32 subctx_id; | ||
569 | u32 runqueue_sel; | ||
570 | }; | ||
571 | |||
572 | struct tegra_vgpu_cmd_msg { | ||
573 | u32 cmd; | ||
574 | int ret; | ||
575 | u64 handle; | ||
576 | union { | ||
577 | struct tegra_vgpu_connect_params connect; | ||
578 | struct tegra_vgpu_channel_hwctx_params channel_hwctx; | ||
579 | struct tegra_vgpu_attrib_params attrib; | ||
580 | struct tegra_vgpu_as_share_params as_share; | ||
581 | struct tegra_vgpu_as_bind_share_params as_bind_share; | ||
582 | struct tegra_vgpu_as_map_params as_map; | ||
583 | struct tegra_vgpu_as_map_ex_params as_map_ex; | ||
584 | struct tegra_vgpu_channel_config_params channel_config; | ||
585 | struct tegra_vgpu_ramfc_params ramfc; | ||
586 | struct tegra_vgpu_ch_ctx_params ch_ctx; | ||
587 | struct tegra_vgpu_zcull_bind_params zcull_bind; | ||
588 | struct tegra_vgpu_cache_maint_params cache_maint; | ||
589 | struct tegra_vgpu_runlist_params runlist; | ||
590 | struct tegra_vgpu_golden_ctx_params golden_ctx; | ||
591 | struct tegra_vgpu_zcull_info_params zcull_info; | ||
592 | struct tegra_vgpu_zbc_set_table_params zbc_set_table; | ||
593 | struct tegra_vgpu_zbc_query_table_params zbc_query_table; | ||
594 | struct tegra_vgpu_gr_bind_ctxsw_buffers_params gr_bind_ctxsw_buffers; | ||
595 | struct tegra_vgpu_mmu_debug_mode mmu_debug_mode; | ||
596 | struct tegra_vgpu_sm_debug_mode sm_debug_mode; | ||
597 | struct tegra_vgpu_reg_ops_params reg_ops; | ||
598 | struct tegra_vgpu_channel_priority_params channel_priority; | ||
599 | struct tegra_vgpu_channel_runlist_interleave_params channel_interleave; | ||
600 | struct tegra_vgpu_channel_timeslice_params channel_timeslice; | ||
601 | struct tegra_vgpu_fecs_trace_filter fecs_trace_filter; | ||
602 | struct tegra_vgpu_channel_set_ctxsw_mode set_ctxsw_mode; | ||
603 | struct tegra_vgpu_channel_free_hwpm_ctx free_hwpm_ctx; | ||
604 | struct tegra_vgpu_gr_ctx_params gr_ctx; | ||
605 | struct tegra_vgpu_channel_bind_gr_ctx_params ch_bind_gr_ctx; | ||
606 | struct tegra_vgpu_tsg_bind_gr_ctx_params tsg_bind_gr_ctx; | ||
607 | struct tegra_vgpu_tsg_bind_unbind_channel_params tsg_bind_unbind_channel; | ||
608 | struct tegra_vgpu_tsg_open_rel_params tsg_open; | ||
609 | struct tegra_vgpu_tsg_open_rel_params tsg_release; | ||
610 | struct tegra_vgpu_tsg_preempt_params tsg_preempt; | ||
611 | struct tegra_vgpu_tsg_timeslice_params tsg_timeslice; | ||
612 | struct tegra_vgpu_tsg_runlist_interleave_params tsg_interleave; | ||
613 | struct tegra_vgpu_read_ptimer_params read_ptimer; | ||
614 | struct tegra_vgpu_set_powergate_params set_powergate; | ||
615 | struct tegra_vgpu_gpu_clk_rate_params gpu_clk_rate; | ||
616 | struct tegra_vgpu_constants_params constants; | ||
617 | struct tegra_vgpu_channel_cyclestats_snapshot_params cyclestats_snapshot; | ||
618 | struct tegra_vgpu_gpu_load_params gpu_load; | ||
619 | struct tegra_vgpu_suspend_resume_contexts suspend_contexts; | ||
620 | struct tegra_vgpu_suspend_resume_contexts resume_contexts; | ||
621 | struct tegra_vgpu_clear_sm_error_state clear_sm_error_state; | ||
622 | struct tegra_vgpu_prof_mgt_params prof_management; | ||
623 | struct tegra_vgpu_perfbuf_mgt_params perfbuf_management; | ||
624 | struct tegra_vgpu_get_timestamps_zipper_params get_timestamps_zipper; | ||
625 | struct tegra_vgpu_get_gpu_freq_table_params get_gpu_freq_table; | ||
626 | struct tegra_vgpu_vsms_mapping_params vsms_mapping; | ||
627 | struct tegra_vgpu_alloc_ctx_header_params alloc_ctx_header; | ||
628 | struct tegra_vgpu_free_ctx_header_params free_ctx_header; | ||
629 | struct tegra_vgpu_map_syncpt_params map_syncpt; | ||
630 | struct tegra_vgpu_tsg_bind_channel_ex_params tsg_bind_channel_ex; | ||
631 | char padding[192]; | ||
632 | } params; | ||
633 | }; | ||
634 | |||
635 | enum { | ||
636 | TEGRA_VGPU_GR_INTR_NOTIFY = 0, | ||
637 | TEGRA_VGPU_GR_INTR_SEMAPHORE_TIMEOUT = 1, | ||
638 | TEGRA_VGPU_GR_INTR_ILLEGAL_NOTIFY = 2, | ||
639 | TEGRA_VGPU_GR_INTR_ILLEGAL_METHOD = 3, | ||
640 | TEGRA_VGPU_GR_INTR_ILLEGAL_CLASS = 4, | ||
641 | TEGRA_VGPU_GR_INTR_FECS_ERROR = 5, | ||
642 | TEGRA_VGPU_GR_INTR_CLASS_ERROR = 6, | ||
643 | TEGRA_VGPU_GR_INTR_FIRMWARE_METHOD = 7, | ||
644 | TEGRA_VGPU_GR_INTR_EXCEPTION = 8, | ||
645 | TEGRA_VGPU_GR_INTR_SEMAPHORE = 9, | ||
646 | TEGRA_VGPU_FIFO_INTR_PBDMA = 10, | ||
647 | TEGRA_VGPU_FIFO_INTR_CTXSW_TIMEOUT = 11, | ||
648 | TEGRA_VGPU_FIFO_INTR_MMU_FAULT = 12, | ||
649 | TEGRA_VGPU_GR_NONSTALL_INTR_SEMAPHORE = 13, | ||
650 | TEGRA_VGPU_FIFO_NONSTALL_INTR_CHANNEL = 14, | ||
651 | TEGRA_VGPU_CE2_NONSTALL_INTR_NONBLOCKPIPE = 15, | ||
652 | TEGRA_VGPU_GR_INTR_SM_EXCEPTION = 16, | ||
653 | }; | ||
654 | |||
655 | struct tegra_vgpu_gr_intr_info { | ||
656 | u32 type; | ||
657 | u32 chid; | ||
658 | }; | ||
659 | |||
660 | struct tegra_vgpu_gr_nonstall_intr_info { | ||
661 | u32 type; | ||
662 | }; | ||
663 | |||
664 | struct tegra_vgpu_fifo_intr_info { | ||
665 | u32 type; | ||
666 | u32 chid; | ||
667 | }; | ||
668 | |||
669 | struct tegra_vgpu_fifo_nonstall_intr_info { | ||
670 | u32 type; | ||
671 | }; | ||
672 | |||
673 | struct tegra_vgpu_ce2_nonstall_intr_info { | ||
674 | u32 type; | ||
675 | }; | ||
676 | |||
677 | enum { | ||
678 | TEGRA_VGPU_FECS_TRACE_DATA_UPDATE = 0 | ||
679 | }; | ||
680 | |||
681 | struct tegra_vgpu_fecs_trace_event_info { | ||
682 | u32 type; | ||
683 | }; | ||
684 | |||
685 | struct tegra_vgpu_channel_event_info { | ||
686 | u32 event_id; | ||
687 | u32 is_tsg; | ||
688 | u32 id; /* channel id or tsg id */ | ||
689 | }; | ||
690 | |||
691 | struct tegra_vgpu_sm_esr_info { | ||
692 | u32 sm_id; | ||
693 | u32 hww_global_esr; | ||
694 | u32 hww_warp_esr; | ||
695 | u64 hww_warp_esr_pc; | ||
696 | u32 hww_global_esr_report_mask; | ||
697 | u32 hww_warp_esr_report_mask; | ||
698 | }; | ||
699 | |||
700 | enum { | ||
701 | |||
702 | TEGRA_VGPU_INTR_GR = 0, | ||
703 | TEGRA_VGPU_INTR_FIFO = 1, | ||
704 | TEGRA_VGPU_INTR_CE2 = 2, | ||
705 | TEGRA_VGPU_NONSTALL_INTR_GR = 3, | ||
706 | TEGRA_VGPU_NONSTALL_INTR_FIFO = 4, | ||
707 | TEGRA_VGPU_NONSTALL_INTR_CE2 = 5, | ||
708 | }; | ||
709 | |||
710 | enum { | ||
711 | TEGRA_VGPU_EVENT_INTR = 0, | ||
712 | TEGRA_VGPU_EVENT_ABORT = 1, | ||
713 | TEGRA_VGPU_EVENT_FECS_TRACE = 2, | ||
714 | TEGRA_VGPU_EVENT_CHANNEL = 3, | ||
715 | TEGRA_VGPU_EVENT_SM_ESR = 4, | ||
716 | }; | ||
717 | |||
718 | struct tegra_vgpu_intr_msg { | ||
719 | unsigned int event; | ||
720 | u32 unit; | ||
721 | union { | ||
722 | struct tegra_vgpu_gr_intr_info gr_intr; | ||
723 | struct tegra_vgpu_gr_nonstall_intr_info gr_nonstall_intr; | ||
724 | struct tegra_vgpu_fifo_intr_info fifo_intr; | ||
725 | struct tegra_vgpu_fifo_nonstall_intr_info fifo_nonstall_intr; | ||
726 | struct tegra_vgpu_ce2_nonstall_intr_info ce2_nonstall_intr; | ||
727 | struct tegra_vgpu_fecs_trace_event_info fecs_trace; | ||
728 | struct tegra_vgpu_channel_event_info channel_event; | ||
729 | struct tegra_vgpu_sm_esr_info sm_esr; | ||
730 | char padding[32]; | ||
731 | } info; | ||
732 | }; | ||
733 | |||
734 | #define TEGRA_VGPU_QUEUE_SIZES \ | ||
735 | 512, \ | ||
736 | sizeof(struct tegra_vgpu_intr_msg) | ||
737 | |||
738 | #endif | ||