diff options
author | Sachit Kadle <skadle@nvidia.com> | 2017-01-24 13:22:13 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-06-19 19:36:26 -0400 |
commit | b3a7c2b305ec6f895dc236f0c5f163bd4cbeb248 (patch) | |
tree | a1df93a947d7f5d60a9e57a69d0058d430844c92 /include | |
parent | 2535c81c6c916f9f2e1224e17e80d240df569e49 (diff) |
gpu: nvgpu: vgpu: add devfreq support
Add devfreq governor support in order to allow frequency scaling
in virtualization config. GPU clock frequency operations are
re-directed to the server over RPC.
Bug 200237433
Change-Id: I1c8e565a4fff36d3456dc72ebb20795b7822650e
Signed-off-by: Sachit Kadle <skadle@nvidia.com>
Reviewed-on: http://git-master/r/1295542
(cherry picked from commit d5c956fc06697eda3829c67cb22987e538213b29)
Reviewed-on: http://git-master/r/1280968
(cherry picked from commit 25e2b3cf7cb5559a6849c0024d42c157564a9be2)
Reviewed-on: http://git-master/r/1321835
(cherry picked from commit f871b52fd3f553d6b6375a3c848fbca272ed8e29)
Reviewed-on: http://git-master/r/1313468
Tested-by: Aparna Das <aparnad@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'include')
-rw-r--r-- | include/linux/tegra_vgpu.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h index 67f51806..4d1e1ac9 100644 --- a/include/linux/tegra_vgpu.h +++ b/include/linux/tegra_vgpu.h | |||
@@ -100,6 +100,8 @@ enum { | |||
100 | TEGRA_VGPU_CMD_SUSPEND_CONTEXTS = 66, | 100 | TEGRA_VGPU_CMD_SUSPEND_CONTEXTS = 66, |
101 | TEGRA_VGPU_CMD_RESUME_CONTEXTS = 67, | 101 | TEGRA_VGPU_CMD_RESUME_CONTEXTS = 67, |
102 | TEGRA_VGPU_CMD_CLEAR_SM_ERROR_STATE = 68, | 102 | TEGRA_VGPU_CMD_CLEAR_SM_ERROR_STATE = 68, |
103 | TEGRA_VGPU_CMD_GET_GPU_CLK_RATE = 69, | ||
104 | TEGRA_VGPU_CMD_GET_GPU_FREQ_TABLE = 70, | ||
103 | TEGRA_VGPU_CMD_PROF_MGT = 72, | 105 | TEGRA_VGPU_CMD_PROF_MGT = 72, |
104 | TEGRA_VGPU_CMD_GET_TIMESTAMPS_ZIPPER = 74, | 106 | TEGRA_VGPU_CMD_GET_TIMESTAMPS_ZIPPER = 74, |
105 | }; | 107 | }; |
@@ -485,6 +487,13 @@ struct tegra_vgpu_prof_mgt_params { | |||
485 | u32 mode; | 487 | u32 mode; |
486 | }; | 488 | }; |
487 | 489 | ||
490 | #define TEGRA_VGPU_GPU_FREQ_TABLE_SIZE 25 | ||
491 | |||
492 | struct tegra_vgpu_get_gpu_freq_table_params { | ||
493 | u32 num_freqs; | ||
494 | u32 freqs[TEGRA_VGPU_GPU_FREQ_TABLE_SIZE]; /* in kHz */ | ||
495 | }; | ||
496 | |||
488 | struct tegra_vgpu_cmd_msg { | 497 | struct tegra_vgpu_cmd_msg { |
489 | u32 cmd; | 498 | u32 cmd; |
490 | int ret; | 499 | int ret; |
@@ -536,6 +545,7 @@ struct tegra_vgpu_cmd_msg { | |||
536 | struct tegra_vgpu_clear_sm_error_state clear_sm_error_state; | 545 | struct tegra_vgpu_clear_sm_error_state clear_sm_error_state; |
537 | struct tegra_vgpu_prof_mgt_params prof_management; | 546 | struct tegra_vgpu_prof_mgt_params prof_management; |
538 | struct tegra_vgpu_get_timestamps_zipper_params get_timestamps_zipper; | 547 | struct tegra_vgpu_get_timestamps_zipper_params get_timestamps_zipper; |
548 | struct tegra_vgpu_get_gpu_freq_table_params get_gpu_freq_table; | ||
539 | char padding[192]; | 549 | char padding[192]; |
540 | } params; | 550 | } params; |
541 | }; | 551 | }; |