diff options
author | Richard Zhao <rizhao@nvidia.com> | 2016-05-10 19:26:40 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-05-31 13:48:10 -0400 |
commit | b0ffd2f0657a11c2fcd7470430465c77ca5c73b9 (patch) | |
tree | eaf8570dc4436f0fd8d97f90996bf06bc61a749f /include | |
parent | 7a134457a840118ed02967a3c0bc4b4f248837ea (diff) |
nvgpu: vgpu: add tsg set interleave support
added a new cmd to support setting tsg interleave level.
Bug 1702773
VFND-1492
Change-Id: Idd9b9c59180b156293ddfc4e2b879d0ea6908388
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1145024
(cherry picked from commit 0929ff1089fbc331b07e17073a46fda4086ae785)
Reviewed-on: http://git-master/r/1150706
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'include')
-rw-r--r-- | include/linux/tegra_vgpu.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h index 706d87e4..9547e35b 100644 --- a/include/linux/tegra_vgpu.h +++ b/include/linux/tegra_vgpu.h | |||
@@ -92,6 +92,7 @@ enum { | |||
92 | TEGRA_VGPU_CMD_TSG_UNBIND_CHANNEL, | 92 | TEGRA_VGPU_CMD_TSG_UNBIND_CHANNEL, |
93 | TEGRA_VGPU_CMD_TSG_PREEMPT, | 93 | TEGRA_VGPU_CMD_TSG_PREEMPT, |
94 | TEGRA_VGPU_CMD_TSG_SET_TIMESLICE, | 94 | TEGRA_VGPU_CMD_TSG_SET_TIMESLICE, |
95 | TEGRA_VGPU_CMD_TSG_SET_RUNLIST_INTERLEAVE, | ||
95 | }; | 96 | }; |
96 | 97 | ||
97 | struct tegra_vgpu_connect_params { | 98 | struct tegra_vgpu_connect_params { |
@@ -379,6 +380,12 @@ struct tegra_vgpu_tsg_timeslice_params { | |||
379 | u32 timeslice_us; | 380 | u32 timeslice_us; |
380 | }; | 381 | }; |
381 | 382 | ||
383 | /* level follows nvgpu.h definitions */ | ||
384 | struct tegra_vgpu_tsg_runlist_interleave_params { | ||
385 | u32 tsg_id; | ||
386 | u32 level; | ||
387 | }; | ||
388 | |||
382 | struct tegra_vgpu_cmd_msg { | 389 | struct tegra_vgpu_cmd_msg { |
383 | u32 cmd; | 390 | u32 cmd; |
384 | int ret; | 391 | int ret; |
@@ -418,6 +425,7 @@ struct tegra_vgpu_cmd_msg { | |||
418 | struct tegra_vgpu_tsg_bind_unbind_channel_params tsg_bind_unbind_channel; | 425 | struct tegra_vgpu_tsg_bind_unbind_channel_params tsg_bind_unbind_channel; |
419 | struct tegra_vgpu_tsg_preempt_params tsg_preempt; | 426 | struct tegra_vgpu_tsg_preempt_params tsg_preempt; |
420 | struct tegra_vgpu_tsg_timeslice_params tsg_timeslice; | 427 | struct tegra_vgpu_tsg_timeslice_params tsg_timeslice; |
428 | struct tegra_vgpu_tsg_runlist_interleave_params tsg_interleave; | ||
421 | char padding[192]; | 429 | char padding[192]; |
422 | } params; | 430 | } params; |
423 | }; | 431 | }; |