diff options
author | Konsta Holtta <kholtta@nvidia.com> | 2015-01-30 08:22:11 -0500 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-04-04 21:05:59 -0400 |
commit | adb33505b21a8e75267bb74d602becf8db51946b (patch) | |
tree | 6b8d674e5c098ec0b85b692c5d50c59c749bc177 /include | |
parent | 24ddf71b9009291b829e6c30eb1b22e8838f7367 (diff) |
gpu: nvgpu: add open channel ioctl to ctrl node
Add the ioctl to open a new gpu channel to also the control node for
improved process startup performance, in addition to the current open
ioctl in the channel node. The new channel fd creation is refactored to
a separate function which is called from both ctrl and channel ioctls.
Bug 1604952
Change-Id: I3357ceec694c0e6d7a85807183884324cb725d3a
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/679516
Reviewed-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'include')
-rw-r--r-- | include/uapi/linux/nvgpu.h | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h index 20acc66a..1e438775 100644 --- a/include/uapi/linux/nvgpu.h +++ b/include/uapi/linux/nvgpu.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * NVGPU Public Interface Header | 2 | * NVGPU Public Interface Header |
3 | * | 3 | * |
4 | * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2015, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -238,6 +238,10 @@ struct nvgpu_gpu_get_tpc_masks_args { | |||
238 | __u64 mask_buf_addr; | 238 | __u64 mask_buf_addr; |
239 | }; | 239 | }; |
240 | 240 | ||
241 | struct nvgpu_gpu_open_channel_args { | ||
242 | __s32 channel_fd; | ||
243 | }; | ||
244 | |||
241 | #define NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE \ | 245 | #define NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE \ |
242 | _IOR(NVGPU_GPU_IOCTL_MAGIC, 1, struct nvgpu_gpu_zcull_get_ctx_size_args) | 246 | _IOR(NVGPU_GPU_IOCTL_MAGIC, 1, struct nvgpu_gpu_zcull_get_ctx_size_args) |
243 | #define NVGPU_GPU_IOCTL_ZCULL_GET_INFO \ | 247 | #define NVGPU_GPU_IOCTL_ZCULL_GET_INFO \ |
@@ -258,9 +262,11 @@ struct nvgpu_gpu_get_tpc_masks_args { | |||
258 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 9, struct nvgpu_gpu_open_tsg_args) | 262 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 9, struct nvgpu_gpu_open_tsg_args) |
259 | #define NVGPU_GPU_IOCTL_GET_TPC_MASKS \ | 263 | #define NVGPU_GPU_IOCTL_GET_TPC_MASKS \ |
260 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 10, struct nvgpu_gpu_get_tpc_masks_args) | 264 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 10, struct nvgpu_gpu_get_tpc_masks_args) |
265 | #define NVGPU_GPU_IOCTL_OPEN_CHANNEL \ | ||
266 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 11, struct nvgpu_gpu_open_channel_args) | ||
261 | 267 | ||
262 | #define NVGPU_GPU_IOCTL_LAST \ | 268 | #define NVGPU_GPU_IOCTL_LAST \ |
263 | _IOC_NR(NVGPU_GPU_IOCTL_GET_TPC_MASKS) | 269 | _IOC_NR(NVGPU_GPU_IOCTL_OPEN_CHANNEL) |
264 | #define NVGPU_GPU_IOCTL_MAX_ARG_SIZE \ | 270 | #define NVGPU_GPU_IOCTL_MAX_ARG_SIZE \ |
265 | sizeof(struct nvgpu_gpu_prepare_compressible_read_args) | 271 | sizeof(struct nvgpu_gpu_prepare_compressible_read_args) |
266 | 272 | ||