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authorRichard Zhao <rizhao@nvidia.com>2017-04-06 20:56:08 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-06-09 17:55:12 -0400
commit914bb78a7dc0687b349310cc28613ea4a4c0be33 (patch)
treeb98060ceb487bba82c3120ca9d4db7403c698f47 /include
parent40ca7cc573430ca4e21fdec4a44394c09d615846 (diff)
gpu: nvgpu: vgpu: move TEGRA_VGPU_ATTRIB_PREEMPT_CTX_SIZE to constants
Also removed deprecated TEGRA_VGPU_ATTRIB_*, but leave a place holder in case someone wants to use this command in future. Jira VFND-3796 Change-Id: Ic36a59db238d276b0e3dd68a9d8ec5834a04333d Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1457497 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'include')
-rw-r--r--include/linux/tegra_vgpu.h27
1 files changed, 1 insertions, 26 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h
index 5d4fa36a..daef7d98 100644
--- a/include/linux/tegra_vgpu.h
+++ b/include/linux/tegra_vgpu.h
@@ -114,32 +114,6 @@ struct tegra_vgpu_channel_hwctx_params {
114 u64 handle; 114 u64 handle;
115}; 115};
116 116
117enum {
118 TEGRA_VGPU_ATTRIB_NUM_CHANNELS = 0, /*deprecated */
119 TEGRA_VGPU_ATTRIB_GOLDEN_CTX_SIZE = 1, /* deprecated */
120 TEGRA_VGPU_ATTRIB_ZCULL_CTX_SIZE = 2, /* deprecated */
121 TEGRA_VGPU_ATTRIB_COMPTAG_LINES = 3, /* deprecated */
122 TEGRA_VGPU_ATTRIB_GPC_COUNT = 4, /* deprecated */
123 TEGRA_VGPU_ATTRIB_MAX_TPC_PER_GPC_COUNT = 5, /* deprecated */
124 TEGRA_VGPU_ATTRIB_MAX_TPC_COUNT = 6, /* deprecated */
125 TEGRA_VGPU_ATTRIB_PMC_BOOT_0 = 7, /* deprecated */
126 TEGRA_VGPU_ATTRIB_L2_SIZE = 8, /* deprecated */
127 TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH = 9, /* deprecated */
128 TEGRA_VGPU_ATTRIB_NUM_FBPS = 10, /* deprecated */
129 TEGRA_VGPU_ATTRIB_FBP_EN_MASK = 11, /* deprecated */
130 TEGRA_VGPU_ATTRIB_MAX_LTC_PER_FBP = 12, /* deprecated */
131 TEGRA_VGPU_ATTRIB_MAX_LTS_PER_LTC = 13, /* deprecated */
132 TEGRA_VGPU_ATTRIB_GPC0_TPC_MASK = 14, /* deprecated */
133 TEGRA_VGPU_ATTRIB_CACHELINE_SIZE = 15, /* deprecated */
134 TEGRA_VGPU_ATTRIB_COMPTAGS_PER_CACHELINE = 16, /* deprecated */
135 TEGRA_VGPU_ATTRIB_SLICES_PER_LTC = 17, /* deprecated */
136 TEGRA_VGPU_ATTRIB_LTC_COUNT = 18, /* deprecated */
137 TEGRA_VGPU_ATTRIB_TPC_COUNT = 19, /* deprecated */
138 TEGRA_VGPU_ATTRIB_GPC0_TPC_COUNT = 20, /* deprecated */
139 TEGRA_VGPU_ATTRIB_MAX_FREQ = 21, /* deprecated */
140 TEGRA_VGPU_ATTRIB_PREEMPT_CTX_SIZE = 64, /* gap to hide T18x IP */
141};
142
143struct tegra_vgpu_attrib_params { 117struct tegra_vgpu_attrib_params {
144 u32 attrib; 118 u32 attrib;
145 u32 value; 119 u32 value;
@@ -458,6 +432,7 @@ struct tegra_vgpu_constants_params {
458 u32 hwpm_ctx_size; 432 u32 hwpm_ctx_size;
459 u8 force_preempt_mode; 433 u8 force_preempt_mode;
460 u32 default_timeslice_us; 434 u32 default_timeslice_us;
435 u32 preempt_ctx_size;
461}; 436};
462 437
463struct tegra_vgpu_channel_cyclestats_snapshot_params { 438struct tegra_vgpu_channel_cyclestats_snapshot_params {