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authorTerje Bergstrom <tbergstrom@nvidia.com>2016-11-08 17:29:14 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2016-11-11 14:47:42 -0500
commit8fa5e7c58ac08fdb2432a4791595278d69827fb0 (patch)
tree18d76c47d66d314206315f1d81adcf8513872d09 /include
parente580e68f2374b3a0b6226eac7fc4e21dbdcbf22c (diff)
gpu: nvgpu: Remove IOCTL FREE_OBJ_CTX
We have never used the IOCTL FREE_OBJ_CTX. Using it leads to context being only partially available, and can lead to use-after-free. Bug 1834225 Change-Id: I9d2b632ab79760f8186d02e0f35861b3a6aae649 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1250004 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'include')
-rw-r--r--include/uapi/linux/nvgpu.h6
1 files changed, 0 insertions, 6 deletions
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h
index a8ba2189..e4f94c16 100644
--- a/include/uapi/linux/nvgpu.h
+++ b/include/uapi/linux/nvgpu.h
@@ -973,10 +973,6 @@ struct nvgpu_alloc_obj_ctx_args {
973 __u64 obj_id; /* output, used to free later */ 973 __u64 obj_id; /* output, used to free later */
974}; 974};
975 975
976struct nvgpu_free_obj_ctx_args {
977 __u64 obj_id; /* obj ctx to free */
978};
979
980struct nvgpu_alloc_gpfifo_args { 976struct nvgpu_alloc_gpfifo_args {
981 __u32 num_entries; 977 __u32 num_entries;
982#define NVGPU_ALLOC_GPFIFO_FLAGS_VPR_ENABLED (1 << 0) /* set owner channel of this gpfifo as a vpr channel */ 978#define NVGPU_ALLOC_GPFIFO_FLAGS_VPR_ENABLED (1 << 0) /* set owner channel of this gpfifo as a vpr channel */
@@ -1216,8 +1212,6 @@ struct nvgpu_preemption_mode_args {
1216 _IOWR(NVGPU_IOCTL_MAGIC, 107, struct nvgpu_submit_gpfifo_args) 1212 _IOWR(NVGPU_IOCTL_MAGIC, 107, struct nvgpu_submit_gpfifo_args)
1217#define NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX \ 1213#define NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX \
1218 _IOWR(NVGPU_IOCTL_MAGIC, 108, struct nvgpu_alloc_obj_ctx_args) 1214 _IOWR(NVGPU_IOCTL_MAGIC, 108, struct nvgpu_alloc_obj_ctx_args)
1219#define NVGPU_IOCTL_CHANNEL_FREE_OBJ_CTX \
1220 _IOR(NVGPU_IOCTL_MAGIC, 109, struct nvgpu_free_obj_ctx_args)
1221#define NVGPU_IOCTL_CHANNEL_ZCULL_BIND \ 1215#define NVGPU_IOCTL_CHANNEL_ZCULL_BIND \
1222 _IOWR(NVGPU_IOCTL_MAGIC, 110, struct nvgpu_zcull_bind_args) 1216 _IOWR(NVGPU_IOCTL_MAGIC, 110, struct nvgpu_zcull_bind_args)
1223#define NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER \ 1217#define NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER \