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authorsujeet baranwal <sbaranwal@nvidia.com>2015-02-19 13:34:51 -0500
committerDan Willemsen <dwillemsen@nvidia.com>2015-04-04 21:08:16 -0400
commit8d1ab756ed8a7f4d3138dc5da9d2de9f52915261 (patch)
tree969a5a5aead991570d8c8c56acd41adb2103b8f5 /include
parentac205be1d31b00c5641df81d53f2da5f143d3354 (diff)
gpu: nvgpu: ioctl for flushing GPU L2
CUDA devtools need to be able to flush the GPU's cache in a sideband fashion and so cannot use methods. This change implements an nvgpu_gpu_ioctl to flush and optionally invalidate the GPU's L2 cache and flush fb. Change-Id: Ib06a0bc8d8880ffbfe4b056518cc3c3df0cc4988 Signed-off-by: sujeet baranwal <sbaranwal@nvidia.com> Signed-off-by: Mayank Kaushik <mkaushik@nvidia.com> Reviewed-on: http://git-master/r/671809 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'include')
-rw-r--r--include/uapi/linux/nvgpu.h13
1 files changed, 11 insertions, 2 deletions
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h
index ebeacf9b..3c53ba94 100644
--- a/include/uapi/linux/nvgpu.h
+++ b/include/uapi/linux/nvgpu.h
@@ -242,6 +242,14 @@ struct nvgpu_gpu_open_channel_args {
242 __s32 channel_fd; 242 __s32 channel_fd;
243}; 243};
244 244
245/* L2 cache writeback, optionally invalidate clean lines and flush fb */
246struct nvgpu_gpu_l2_fb_args {
247 __u32 l2_flush:1;
248 __u32 l2_invalidate:1;
249 __u32 fb_flush:1;
250 __u32 reserved;
251} __packed;
252
245#define NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE \ 253#define NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE \
246 _IOR(NVGPU_GPU_IOCTL_MAGIC, 1, struct nvgpu_gpu_zcull_get_ctx_size_args) 254 _IOR(NVGPU_GPU_IOCTL_MAGIC, 1, struct nvgpu_gpu_zcull_get_ctx_size_args)
247#define NVGPU_GPU_IOCTL_ZCULL_GET_INFO \ 255#define NVGPU_GPU_IOCTL_ZCULL_GET_INFO \
@@ -264,13 +272,14 @@ struct nvgpu_gpu_open_channel_args {
264 _IOWR(NVGPU_GPU_IOCTL_MAGIC, 10, struct nvgpu_gpu_get_tpc_masks_args) 272 _IOWR(NVGPU_GPU_IOCTL_MAGIC, 10, struct nvgpu_gpu_get_tpc_masks_args)
265#define NVGPU_GPU_IOCTL_OPEN_CHANNEL \ 273#define NVGPU_GPU_IOCTL_OPEN_CHANNEL \
266 _IOWR(NVGPU_GPU_IOCTL_MAGIC, 11, struct nvgpu_gpu_open_channel_args) 274 _IOWR(NVGPU_GPU_IOCTL_MAGIC, 11, struct nvgpu_gpu_open_channel_args)
275#define NVGPU_GPU_IOCTL_FLUSH_L2 \
276 _IOWR(NVGPU_DBG_GPU_IOCTL_MAGIC, 12, struct nvgpu_gpu_l2_fb_args)
267 277
268#define NVGPU_GPU_IOCTL_LAST \ 278#define NVGPU_GPU_IOCTL_LAST \
269 _IOC_NR(NVGPU_GPU_IOCTL_OPEN_CHANNEL) 279 _IOC_NR(NVGPU_GPU_IOCTL_FLUSH_L2)
270#define NVGPU_GPU_IOCTL_MAX_ARG_SIZE \ 280#define NVGPU_GPU_IOCTL_MAX_ARG_SIZE \
271 sizeof(struct nvgpu_gpu_prepare_compressible_read_args) 281 sizeof(struct nvgpu_gpu_prepare_compressible_read_args)
272 282
273
274/* 283/*
275 * /dev/nvhost-tsg-gpu device 284 * /dev/nvhost-tsg-gpu device
276 * 285 *