Merge remote-tracking branch 'remotes/origin/dev/merge-nvgpu-t18x-into-nvgpu' into dev-kernel

Merge T186 - gp10b/gp106 code into common nvgpu repo

Bug 200266498

Change-Id: Ibf100ee38010cbed85c149b69b99147256f9a005
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>

2 files changed, 116 insertions, 0 deletions

diff --git a/include/linux/tegra_vgpu_t18x.h b/include/linux/tegra_vgpu_t18x.h
new file mode 100644
index 00000000..121f4103
--- /dev/null
+++ b/include/linux/tegra_vgpu_t18x.h
@@ -0,0 +1,42 @@
+/*
+ * Tegra GPU Virtualization Interfaces to Server
+ *
+ * Copyright (c) 2015, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __TEGRA_VGPU_T18X_H
+#define __TEGRA_VGPU_T18X_H
+
+enum {
+        TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN,
+        TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL,
+        TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL,
+        TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB,
+        TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_LAST
+};
+
+enum {
+        TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_WFI,
+        TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_GFX_GFXP,
+        TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CTA,
+        TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CILP,
+        TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_LAST
+};
+
+enum {
+        TEGRA_VGPU_ATTRIB_PREEMPT_CTX_SIZE = 64
+};
+
+#endif
diff --git a/include/uapi/linux/nvgpu-t18x.h b/include/uapi/linux/nvgpu-t18x.h
new file mode 100644
index 00000000..777f1553
--- /dev/null
+++ b/include/uapi/linux/nvgpu-t18x.h
@@ -0,0 +1,74 @@
+/*
+ * NVGPU Public Interface Header
+ *
+ * Copyright (c) 2011-2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+/* This file is meant to extend nvgpu.h, not replace it
+ * as such, be sure that nvgpu.h is actually the file performing the
+ * inclusion, to the extent that's possible.
+ */
+#ifndef _UAPI__LINUX_NVGPU_IOCTL_H
+#    error "This file is to be included within nvgpu.h only."
+#endif
+
+#ifndef _UAPI__LINUX_NVGPU_T18X_IOCTL_H_
+#define _UAPI__LINUX_NVGPU_T18X_IOCTL_H_
+
+#define NVGPU_GPU_ARCH_GP100 0x00000130
+#define NVGPU_GPU_IMPL_GP104 0x00000004
+#define NVGPU_GPU_IMPL_GP106 0x00000006
+#define NVGPU_GPU_IMPL_GP10B 0x0000000B
+
+/*
+ * this flag is used in struct nvgpu_as_map_buffer_ex_args
+ * to specify IO coherence
+ */
+#define NVGPU_AS_MAP_BUFFER_FLAGS_IO_COHERENT       (1 << 4)
+
+/*
+ * this flag is used in struct nvgpu_alloc_gpfifo_args
+ * to enable re-playable faults for that channel
+ */
+#define NVGPU_ALLOC_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE   (1 << 2)
+
+/* Flags in nvgpu_alloc_obj_ctx_args.flags */
+#define NVGPU_ALLOC_OBJ_FLAGS_GFXP              (1 << 1)
+#define NVGPU_ALLOC_OBJ_FLAGS_CILP              (1 << 2)
+
+/* Flags in nvgpu_preemption_mode_args.graphics_preempt_flags */
+#define NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP     (1 << 1)
+/* Flags in nvgpu_preemption_mode_args.compute_preempt_flags */
+#define NVGPU_COMPUTE_PREEMPTION_MODE_CILP      (1 << 2)
+
+/* SM LRF ECC is enabled */
+#define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF      (1ULL << 60)
+/* SM SHM ECC is enabled */
+#define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM      (1ULL << 61)
+/* TEX ECC is enabled */
+#define NVGPU_GPU_FLAGS_ECC_ENABLED_TEX         (1ULL << 62)
+/* L2 ECC is enabled */
+#define NVGPU_GPU_FLAGS_ECC_ENABLED_LTC         (1ULL << 63)
+/* All types of ECC are enabled */
+#define NVGPU_GPU_FLAGS_ALL_ECC_ENABLED \
+                                (NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF |   \
+                                NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM |    \
+                                NVGPU_GPU_FLAGS_ECC_ENABLED_TEX    |    \
+                                NVGPU_GPU_FLAGS_ECC_ENABLED_LTC)
+
+/* Channel event_id in nvgpu_channel_events_ctrl_ext_args */
+#define NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_STARTED    3
+#define NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_COMPLETE   4
+
+#endif /* _UAPI__LINUX_NVGPU_T18X_IOCTL_H_ */
+
+