diff options
author | Richard Zhao <rizhao@nvidia.com> | 2016-05-09 20:24:49 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-05-31 13:47:47 -0400 |
commit | 7a134457a840118ed02967a3c0bc4b4f248837ea (patch) | |
tree | 9d633695abe78b95481b459a77cc905af18e9d17 /include | |
parent | d707c5a444e024e1184213a75f44a73dbb1707d2 (diff) |
gpu: nvgpu: vgpu: add tsg set timeslice support
Bug 1702773
JIRA VFND-1496
Change-Id: Ice570df78d974fa59f2a932caf0e6249b13493a1
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1144929
(cherry picked from commit 8b6ec996f3773e497a040a8fe4148e01e8dc35fa)
Reviewed-on: http://git-master/r/1150705
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'include')
-rw-r--r-- | include/linux/tegra_vgpu.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h index bdaabf29..706d87e4 100644 --- a/include/linux/tegra_vgpu.h +++ b/include/linux/tegra_vgpu.h | |||
@@ -91,6 +91,7 @@ enum { | |||
91 | TEGRA_VGPU_CMD_TSG_BIND_CHANNEL, | 91 | TEGRA_VGPU_CMD_TSG_BIND_CHANNEL, |
92 | TEGRA_VGPU_CMD_TSG_UNBIND_CHANNEL, | 92 | TEGRA_VGPU_CMD_TSG_UNBIND_CHANNEL, |
93 | TEGRA_VGPU_CMD_TSG_PREEMPT, | 93 | TEGRA_VGPU_CMD_TSG_PREEMPT, |
94 | TEGRA_VGPU_CMD_TSG_SET_TIMESLICE, | ||
94 | }; | 95 | }; |
95 | 96 | ||
96 | struct tegra_vgpu_connect_params { | 97 | struct tegra_vgpu_connect_params { |
@@ -373,6 +374,11 @@ struct tegra_vgpu_tsg_preempt_params { | |||
373 | u32 tsg_id; | 374 | u32 tsg_id; |
374 | }; | 375 | }; |
375 | 376 | ||
377 | struct tegra_vgpu_tsg_timeslice_params { | ||
378 | u32 tsg_id; | ||
379 | u32 timeslice_us; | ||
380 | }; | ||
381 | |||
376 | struct tegra_vgpu_cmd_msg { | 382 | struct tegra_vgpu_cmd_msg { |
377 | u32 cmd; | 383 | u32 cmd; |
378 | int ret; | 384 | int ret; |
@@ -411,6 +417,7 @@ struct tegra_vgpu_cmd_msg { | |||
411 | struct tegra_vgpu_tsg_bind_gr_ctx_params tsg_bind_gr_ctx; | 417 | struct tegra_vgpu_tsg_bind_gr_ctx_params tsg_bind_gr_ctx; |
412 | struct tegra_vgpu_tsg_bind_unbind_channel_params tsg_bind_unbind_channel; | 418 | struct tegra_vgpu_tsg_bind_unbind_channel_params tsg_bind_unbind_channel; |
413 | struct tegra_vgpu_tsg_preempt_params tsg_preempt; | 419 | struct tegra_vgpu_tsg_preempt_params tsg_preempt; |
420 | struct tegra_vgpu_tsg_timeslice_params tsg_timeslice; | ||
414 | char padding[192]; | 421 | char padding[192]; |
415 | } params; | 422 | } params; |
416 | }; | 423 | }; |