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| author | Seema Khowala <seemaj@nvidia.com> | 2017-06-30 14:45:16 -0400 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-05 06:06:51 -0400 |
| commit | 690d560e65af8096bc391064631c74a3dd14fa89 (patch) | |
| tree | 80d2d74f70810b6977d760aea03687361a3d28d9 /include | |
| parent | a4439aee3a47ed9b966e5864a8e18a2bb13a9bb7 (diff) | |
gpu: nvgpu: gv11b: Use sm dbgr bpt and warp mask 0/1
Instead of assuming mask_0 and mask_1 as consecutive registers,
use mask_1 and mask_0 registers for reading/writing sm dbgr warp
and bpt mask registers
JIRA GPUT19X-75
Change-Id: Ib6843d13828d899d4bd3f12bdf6701325ea760fd
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1511736
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions