gpu: nvgpu: Determine ECC-enabled units for GP10B

Determine ECC-enabled units for GP10B by reading fuses/registers.

Bug 1637486

Change-Id: I6431709e3c405d6156dd96438df14d4054b48644
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/780992
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1120463
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 16 insertions, 1 deletions

diff --git a/include/uapi/linux/nvgpu-t18x.h b/include/uapi/linux/nvgpu-t18x.h
index b2a75143..6116ec61 100644
--- a/include/uapi/linux/nvgpu-t18x.h
+++ b/include/uapi/linux/nvgpu-t18x.h
@@ -1,7 +1,7 @@
 /*
  * NVGPU Public Interface Header
  *
- * Copyright (c) 2011-2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2016, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -43,6 +43,21 @@
 #define NVGPU_ALLOC_OBJ_FLAGS_GFXP              (1 << 1)
 #define NVGPU_ALLOC_OBJ_FLAGS_CILP              (1 << 2)
 
+/* SM LRF ECC is enabled */
+#define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF      (1ULL << 60)
+/* SM SHM ECC is enabled */
+#define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM      (1ULL << 61)
+/* TEX ECC is enabled */
+#define NVGPU_GPU_FLAGS_ECC_ENABLED_TEX         (1ULL << 62)
+/* L2 ECC is enabled */
+#define NVGPU_GPU_FLAGS_ECC_ENABLED_LTC         (1ULL << 63)
+/* All types of ECC are enabled */
+#define NVGPU_GPU_FLAGS_ALL_ECC_ENABLED \
+                                (NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF |   \
+                                NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM |    \
+                                NVGPU_GPU_FLAGS_ECC_ENABLED_TEX    |    \
+                                NVGPU_GPU_FLAGS_ECC_ENABLED_LTC)
+
 #endif /* _UAPI__LINUX_NVGPU_T18X_IOCTL_H_ */