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authorAparna Das <aparnad@nvidia.com>2017-11-30 04:08:52 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2017-12-30 21:50:40 -0500
commit4f67a794ddbb9e5c1ce66461fabdf3f27708945a (patch)
tree7e4d379d6bb10792060a55b5648d53dee38ea69d /include
parentb983c67d846547d047156d12a64cb7b216598738 (diff)
gpu: nvgpu: vgpu: add io coherency support
Modify command message parameter to support io coherency. Jira EVLR-2025 Change-Id: I38b21c72d85f559555c4d97dab73d0f715ecc655 Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1614388 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'include')
-rw-r--r--include/linux/tegra_vgpu.h5
1 files changed, 4 insertions, 1 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h
index 5c81e8c9..7b5c9e11 100644
--- a/include/linux/tegra_vgpu.h
+++ b/include/linux/tegra_vgpu.h
@@ -160,6 +160,9 @@ struct tegra_vgpu_as_map_params {
160 u32 ctag_offset; 160 u32 ctag_offset;
161}; 161};
162 162
163#define TEGRA_VGPU_MAP_CACHEABLE (1 << 0)
164#define TEGRA_VGPU_MAP_IO_COHERENT (1 << 1)
165
163struct tegra_vgpu_as_map_ex_params { 166struct tegra_vgpu_as_map_ex_params {
164 u64 handle; 167 u64 handle;
165 u64 gpu_va; 168 u64 gpu_va;
@@ -168,7 +171,7 @@ struct tegra_vgpu_as_map_ex_params {
168 u8 pgsz_idx; 171 u8 pgsz_idx;
169 u8 iova; 172 u8 iova;
170 u8 kind; 173 u8 kind;
171 u8 cacheable; 174 u32 flags;
172 u8 clear_ctags; 175 u8 clear_ctags;
173 u8 prot; 176 u8 prot;
174 u32 ctag_offset; 177 u32 ctag_offset;