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authorAparna Das <aparnad@nvidia.com>2017-11-30 04:11:36 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2018-01-12 16:26:41 -0500
commit47c794ab5238482d15448a862dbd63530f261952 (patch)
tree7d68c36cb4bc59ab24a304a154234cfa2e39ac80 /include
parent9dd3bb2e62c321bb48c14f3e76c00a754cd12c5f (diff)
gpu: nvgpu: vgpu: add l3 allocation support
Modify rpc command parameter to support l3 cache allocation. Jira EVLR-1752 Change-Id: I1be00e04ee01c0763f46c0d0da6a112316cc7e1d Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1616566 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'include')
-rw-r--r--include/linux/tegra_vgpu.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h
index 105870dc..9980f4bc 100644
--- a/include/linux/tegra_vgpu.h
+++ b/include/linux/tegra_vgpu.h
@@ -163,6 +163,7 @@ struct tegra_vgpu_as_map_params {
163 163
164#define TEGRA_VGPU_MAP_CACHEABLE (1 << 0) 164#define TEGRA_VGPU_MAP_CACHEABLE (1 << 0)
165#define TEGRA_VGPU_MAP_IO_COHERENT (1 << 1) 165#define TEGRA_VGPU_MAP_IO_COHERENT (1 << 1)
166#define TEGRA_VGPU_MAP_L3_ALLOC (1 << 2)
166 167
167struct tegra_vgpu_as_map_ex_params { 168struct tegra_vgpu_as_map_ex_params {
168 u64 handle; 169 u64 handle;