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| author | Seema Khowala <seemaj@nvidia.com> | 2017-03-21 14:22:57 -0400 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-03-23 12:34:13 -0400 |
| commit | 40d2f609032a5b492decd0da4c5f50e00f765f37 (patch) | |
| tree | ac3d783272ba0d00d7f00decbc3e9dff7fdf3a6b /include | |
| parent | d409d7ebc136470906b861f3bebb7da63e1557e6 (diff) | |
gpu: nvgpu: gv11b: implement init_pbdma_intr_desc fifo ops
Init device_fatal, channel_fatal and restartable fifo intr pbdma s/w
variables for pbdma_intr_0 interrupt masks.
pbdma_intr_0 field changes for gv11b:-
bit 8(lbreq) does not exists in hw.
bit 28 (syncpoint_illegal)is removed in hw.
bit 20 is reused for clear_faulted_error in hw.
bit 24 (eng_reset) and bit 25 (semaphore) always existed in hw
but never handled in s/w. These are added as channel fatal.
JIRA GPUT19X-47
Change-Id: I13673430408f1cf7ef762075a29b94196f79a349
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1325401
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions