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authorPeter Daifuku <pdaifuku@nvidia.com>2016-03-09 22:10:20 -0500
committerTerje Bergstrom <tbergstrom@nvidia.com>2016-04-07 14:05:49 -0400
commit37155b65f1dd6039bdef92f513d86640956bc12c (patch)
tree1deb57523c3acc445996c642da6ac96e1cf7c355 /include
parent6675c03603669c667c6ffec34567eaf101a2d09d (diff)
gpu: nvgpu: support for hwpm context switching
Add support for hwpm context switching Bug 1648200 Change-Id: I482899bf165cd2ef24bb8617be16df01218e462f Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1120450 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'include')
-rw-r--r--include/uapi/linux/nvgpu.h14
1 files changed, 13 insertions, 1 deletions
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h
index 45d1c217..a75a5ae0 100644
--- a/include/uapi/linux/nvgpu.h
+++ b/include/uapi/linux/nvgpu.h
@@ -647,8 +647,20 @@ struct nvgpu_dbg_gpu_set_next_stop_trigger_type_args {
647 _IOWR(NVGPU_DBG_GPU_IOCTL_MAGIC, 12, struct nvgpu_dbg_gpu_set_next_stop_trigger_type_args) 647 _IOWR(NVGPU_DBG_GPU_IOCTL_MAGIC, 12, struct nvgpu_dbg_gpu_set_next_stop_trigger_type_args)
648 648
649 649
650/* PM Context Switch Mode */
651#define NVGPU_DBG_GPU_HWPM_CTXSW_MODE_NO_CTXSW (0x00000000)
652#define NVGPU_DBG_GPU_HWPM_CTXSW_MODE_CTXSW (0x00000001)
653
654struct nvgpu_dbg_gpu_hwpm_ctxsw_mode_args {
655 __u32 mode;
656 __u32 reserved;
657};
658
659#define NVGPU_DBG_GPU_IOCTL_HWPM_CTXSW_MODE \
660 _IOWR(NVGPU_DBG_GPU_IOCTL_MAGIC, 13, struct nvgpu_dbg_gpu_hwpm_ctxsw_mode_args)
661
650#define NVGPU_DBG_GPU_IOCTL_LAST \ 662#define NVGPU_DBG_GPU_IOCTL_LAST \
651 _IOC_NR(NVGPU_DBG_GPU_IOCTL_SET_NEXT_STOP_TRIGGER_TYPE) 663 _IOC_NR(NVGPU_DBG_GPU_IOCTL_HWPM_CTXSW_MODE)
652 664
653#define NVGPU_DBG_GPU_IOCTL_MAX_ARG_SIZE \ 665#define NVGPU_DBG_GPU_IOCTL_MAX_ARG_SIZE \
654 sizeof(struct nvgpu_dbg_gpu_perfbuf_map_args) 666 sizeof(struct nvgpu_dbg_gpu_perfbuf_map_args)